Abstract: A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.

Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Abstract: Debugging a graphics application executing on a target device. The graphics application may execute CPU instructions to generate graphics commands to graphics hardware for generation of graphics on a display. A breakpoint for the graphics application may be detected at a first time. In response to detecting the breakpoint, one or more graphics commands which were executed by the graphics hardware proximate to the first time may be displayed. Additionally, source code corresponding to CPU instructions which generated the one or more graphics commands may be displayed.

Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Abstract: The invention relates to a device and a method (100) for determining a technical incident risk value in an infrastructure (5), said method comprising: a step of receiving (120) performance indicator values, a step of identifying (140) anomalous performance indicators, so as to identify abnormal values, and identifying performance indicators associated with these abnormal values, a step of determining (150) at-risk indicators, comprising an identification of performance indicators of the computing infrastructure that are correlated with the identified anomalous indicators, a step of creating (160) an augmented anomalies vector, comprising the identifiers of the identified anomalous indicators and the identifiers of the determined at-risk indicators, a determination step (170), comprising the comparison of the augmented anomalies vector with predetermined technical incident reference data.

Abstract: The invention relates to a method and a device for determining an estimated duration before a technical incident, said method comprising: a step (120) of receiving performance indicator values, a step (140) of identifying anomalous performance indicators, a step (150) of identifying first at-risk indicators, a step (160) of identifying other at-risk indicators, and a step (170) of determining an estimated duration before a technical incident comprising a calculation, from the anomalous indicators and at-risk indicators identified, of a shorter path leading to a risk of technical incident, and a calculation of an estimated duration before a technical incident, said estimated duration before a technical incident being calculated from the values of duration before becoming anomalous between correlated performance indicators for each of the performance indicators constituting the shortest path calculated.

Abstract: Debugging a graphics application executing on a target device. The graphics application may execute central processing unit (CPU) instructions to generate graphics commands to graphics hardware for generation of graphics on a display. A breakpoint for the graphics application may be detected at a first time. In response to detecting the breakpoint, one or more graphics commands which were executed by the graphics hardware proximate to the first time may be displayed. Additionally, source code corresponding to CPU instructions which generated the one or more graphics commands may be displayed.

Abstract: A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Abstract: This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Abstract: It is described a system and a method for respiratory activity analysis comprising the use of Respiratory Inductance Plethysmography (RIP). In particular, a wearable system for extracting physiological parameters of a person by measuring at least one plethysmographic signal is disclosed. The system comprises: a wearable garment fitting a body part of the person; at least one wire supported by or embedded into the garment, each wire forming a loop around the body part when the person wears the garment for measuring a plethysmographic signal; and an electronic device supported by or fixed on the garment and including a Colpitts oscillator connected to each wire loop, wherein the Colpitts oscillator has an optimal frequency band from 1 MHz to 15 MHz for extracting the plethysmographic signal measured by each wire, the electronic device converting analog information measured by the Colpitts oscillator into digital analyzable information.

Abstract: Disclosed is a system for a facility supporting an access controller, at least one ingress card reader and an auto-enrollment type controller including a front panel having a single button, a controller board, a terminal block for connecting at least the one ingress card reader to the auto-enrollment type controller board and to connect the auto-enrollment type controller to door locks, and a mounting plate, with the auto-enrollment type controller being configured by a user according to operational requirements of the facility by the user asserting the button for a defined period of time.

Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.

Abstract: A computer device comprises a first processing device; a plurality of memory circuits, a first one of which comprises one or more other processing devices; a data bus coupling the first processing device to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processing device and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting the first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Abstract: Debugging a graphics application executing on a target device. The graphics application may execute CPU instructions to generate graphics commands to graphics hardware for generation of graphics on a display. A breakpoint for the graphics application may be detected at a first time. In response to detecting the breakpoint, one or more graphics commands which were executed by the graphics hardware proximate to the first time may be displayed. Additionally, source code corresponding to CPU instructions which generated the one or more graphics commands may be displayed.

Abstract: Debugging a graphics application executing on a target device. The graphics application may execute CPU instructions to generate graphics commands to graphics hardware for generation of graphics on a display. A breakpoint for the graphics application may be detected at a first time. In response to detecting the breakpoint, one or more graphics commands which were executed by the graphics hardware proximate to the first time may be displayed. Additionally, source code corresponding to CPU instructions which generated the one or more graphics commands may be displayed.

Abstract: A memory circuit having: a memory array including one or more memory banks (418); a first processor (420); and a processor control interface for receiving data processing commands directed to the first processor from a central processor (P1, P2), the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.

Abstract: Analyzing an application executing on a target device. An application may be executed on a target device. Low cost measurement may be gathered regarding the application executing on the target device. In response to a trigger, high cost measurement data may be gathered regarding the application executing on the target device. The high cost measurement data may include graphics commands provided by the application. The graphics commands and related information may be stored and provided to a host. The host may modify the graphics commands to perform experiments to determine performance issues of the application executing on the target device. The host may determine whether the performance is limited by the CPU or the GPU and may determine specific operations that are causing performance issues. The host may provide suggestions for overcoming the performance issues.

Abstract: The present relates to a washable interconnection patch, a connection assembly, and an intelligent washable garment equipped therewith. The patch receives and interconnects wires to a cable. The patch comprises two matching pieces interlocking together so as to define there between two opposite apertures. One of the apertures is adapted to receive and hold the wires, and the other aperture is adapted to receive and hold the cable. One of the two matching pieces defines on an interior face a channel to interconnect the wires to the cables. The connection assembly comprises a male connector and a female connector. The male connector defines a series of independent connection points along a length thereof. The female connector is adapted to receive the male connector, and defines along a length of an inner surface thereof a series of contact points. When the male connector is inserted within the female connector, the connection points and the contact points are aligned and in contact together.