Patents by Inventor Jean-Francois Damlencourt

Jean-Francois Damlencourt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622640
    Abstract: The present patent application relates to a device for a lithium electrochemical generator, said device comprising a band (100) of electrical insulating material including at least one polymer, and at least one metallic layer (102) which forms a current collector and is deposited on at least one of the two main faces in the central part of the band. The central part (100C) of the band comprises a plurality of holes (101) emerging on its two opposite main faces, said holes being filled at least partially with a metal that is continuous with each deposited metallic layer. The periphery of the band (100P) is devoid of metallic layer and at least one metallic layer is covered with an electrode of lithium insertion material.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 14, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Damlencourt, Marianne Chami
  • Patent number: 9991548
    Abstract: The present invention relates to a bipolar battery with at least two electrochemical cells stacked one above the other, each collector comprising at its periphery at least one bead of an electrical insulating material also constituting a peripheral zone of the electrolyte-leaktight wall. According to the invention, each leaktight wall is constituted of at least one bead consisting of a honeycomb matrix, the matrix being covered, on each of its two main faces, with a layer or leaf made of heat-sealing and electrically insulating material, each layer or leaf being heat-sealed to one of the current collectors, the heat-sealing and electrically insulating material filling at least partly the cells of the honeycomb while interconnecting the two layers or leafs.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 5, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Damlencourt, Gilles Moreau
  • Publication number: 20160020482
    Abstract: The present invention relates to a bipolar battery with at least two electrochemical cells stacked one above the other, each collector comprising at its periphery at least one bead of an electrical insulating material also constituting a peripheral zone of the electrolyte-leaktight wall. According to the invention, each leaktight wall is constituted of at least one bead consisting of a honeycomb matrix, the matrix being covered, on each of its two main faces, with a layer or leaf made of heat-sealing and electrically insulating material, each layer or leaf being heat-sealed to one of the current collectors, the heat-sealing and electrically insulating material filling at least partly the cells of the honeycomb while interconnecting the two layers or leafs.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 21, 2016
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Damlencourt, Gilles Moreau
  • Publication number: 20150180038
    Abstract: The present invention relates to a bipolar battery comprising at least two electrochemical cells (C1, C2) stacked on top of one another, each collector (13, 21) comprising on its periphery at least one bead (23) of an electrically insulating material also forming a peripheral zone of the wall impermeable to the electrolyte. According to the invention, each impermeable wall is obtained by a technique chosen from direct bonding, anodic bonding between a bead of the bipolar collector and the bead of the adjacent collector, and eutectic bonding between a layer made of metal or a eutectic metal alloy deposited on a bead of the bipolar collector and a layer made of metal or eutectic metal alloy deposited on a bead of the adjacent collector.
    Type: Application
    Filed: July 3, 2013
    Publication date: June 25, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Damlencourt, Emmanuel Augendre, Frank Fournel
  • Publication number: 20150155564
    Abstract: The present patent application relates to a device for a lithium electrochemical generator, said device comprising a band (100) of electrical insulating material including at least one polymer, and at least one metallic layer (102) which forms a current collector and is deposited on at least one of the two main faces in the central part of the band. The central part (100C) of the band comprises a plurality of holes (101) emerging on its two opposite main faces, said holes being filled at least partially with a metal that is continuous with each deposited metallic layer. The periphery of the band (100P) is devoid of metallic layer and at least one metallic layer is covered with an electrode of lithium insertion material.
    Type: Application
    Filed: July 1, 2013
    Publication date: June 4, 2015
    Inventors: Marianne Chami, Jean-Francois Damlencourt
  • Patent number: 9040391
    Abstract: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 26, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-François Damlencourt, Benjamin Vincent
  • Patent number: 8513125
    Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Commissariat a l'energie atomique et aux alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Michel Heitzmann
  • Patent number: 8349667
    Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 8, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Thierry Poiroux
  • Patent number: 8247313
    Abstract: A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: August 21, 2012
    Assignees: Commissariat a l'Energie Atomique, STMicroelectronics (Crolles 2) SAS
    Inventors: Benjamin Vincent, Jean-Francois Damlencourt, Yves Morand
  • Patent number: 7989327
    Abstract: A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si1-xGex layer is formed on a superficial layer of silicon having a buried electrical insulating layer. A silicon oxide layer is formed on the Si1-xGex layer. The resulting stack of silicon, Si1-xGex and silicon oxide layers is etched up to the buried insulating layer leaving an island of the stack, or up to the superficial layer leaving a zone of silicon and an island of the stack. A mask is formed to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island. The germanium of the Si1-xGex layer is condensed on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the insulating layer, with a silicon oxide layer on top of it.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 2, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Benjamin Vincent, Laurent Clavelier, Jean-Francois Damlencourt
  • Patent number: 7972971
    Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0<y?1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si1-yGey based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: July 5, 2011
    Assignees: Commissariat A l'Energie Atomique, STMicroelectronics SA
    Inventors: Jean-Francois Damlencourt, Yves Morand, Laurent Clavelier
  • Publication number: 20110070734
    Abstract: The invention relates to a method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 24, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
    Inventors: Emeline SARACCO, Jean-Francois Damlencourt, Michel Heitzmann
  • Publication number: 20110059598
    Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 10, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emeline SARACCO, Jean-Francois DAMLENCOURT, Thierry POIROUX
  • Patent number: 7759175
    Abstract: The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: July 20, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Laurent Clavelier, Cyrille Le Royer, Jean-François Damlencourt
  • Publication number: 20100044836
    Abstract: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
    Type: Application
    Filed: August 12, 2009
    Publication date: February 25, 2010
    Applicant: Commissariat A L'Energie Atomique
    Inventors: Jean-François Damlencourt, Benjamin Vincent
  • Publication number: 20100035414
    Abstract: A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors.
    Type: Application
    Filed: February 7, 2008
    Publication date: February 11, 2010
    Applicants: Commissariat A L'Energie Atomique, Stmicroelectronics (Crolles 2) Sas
    Inventors: Benjamin Vincent, Jean-Francois Damlencourt, Yves Morand
  • Patent number: 7648893
    Abstract: A method for manufacturing a semiconductor including the steps of supplying a substrate having a support with one face supporting a strained silicon thin layer; forming a first mask on a portion of the strained silicon thin layer; epitaxy of Si1-xGex on the portion of the layer not masked by the first mask; condensating germanium to obtain a strained germanium layer, the strained germanium layer then covered by a silicon oxide layer; eliminating the first mask and of the silicon oxide layer thereby exposing a semi-conducting thin layer; forming a second mask on the semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the exposing a remaining strained germanium portion; epitaxial growing germanium on the remaining strained germanium portion; and removing the second mask.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 19, 2010
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Jean-Francois Damlencourt, Laurent Clavelier
  • Patent number: 7601570
    Abstract: A method for producing a microelectronic device having one or more Si1?zGez based semiconductor wire(s) (with 0<z?1), including: a) thermal oxidation of at least a portion of a Si1?xGex-based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si1?yGey-based semiconductor zone (with 0<y<1 and x<y), b) lateral thermal oxidation of the sides of one or more so-called semiconductor connection blocks from the Si1?yGey-based semiconductor zone and connecting a semiconductor block intended to form a transistor source region and another block intended to form a transistor drain region so as to reduce the semiconductor connection blocks in at least one direction parallel to the main plane of the support and to form one or more Si1?zGez-based semiconductor wire(s) (with 0<y<1 and y<z).
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: October 13, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Jean-Francois Damlencourt
  • Patent number: 7598145
    Abstract: A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0<y?1) that have different respective Germanium contents.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: October 6, 2009
    Assignees: Commissariat a l 'Energie Atomique, STMicroelectronics SA
    Inventors: Jean-Francois Damlencourt, Yves Morand, Laurent Clavelier
  • Publication number: 20090170295
    Abstract: The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 2, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Benjamin Vincent, Laurent Clavelier, Jean-Francois Damlencourt