Abstract: A particle transporter based on travelling-wave dielectrophoresis is provided. The particle transporter includes a common electrode, a plurality of left switch electrodes and a plurality of right switch electrodes. The left switch electrodes and the right switch electrodes are respectively disposed adjacent to different ends at one side of the common electrode. The left switch electrodes are disposed on the substrate along a first straight-line direction. The left switch electrodes are parallel to the common electrode and provide a left switch channel to transport a plurality of particles. The right switch electrodes are disposed on the substrate along a second straight-line direction. The right switch electrodes are parallel to the common electrode and provide a right switch channel to transport the particles.

Abstract: A particle transporter based on travelling-wave dielectrophoresis is provided. The particle transporter includes a first collection electrode and a second collection electrode on a substrate. The first collection electrode has a first dentate portion. The second collection electrode is located adjacent to the first dentate portion of the first collection electrode. The second collection electrode has a second dentate portion at a side adjacent to the first dentate portion. Where, a particle collection space is formed around tips of the first dentate portion and the second dentate portion.

Abstract: A signal conversion device, a radio frequency identification (RFID) tag, and a method for operating the RFID tag. The RFID tag has an electrically erasable programmable read-only memory module for storing RFID tag information and transmitting the RFID tag information; an information comparison module coupled to the electrically erasable programmable for receiving the RFID tag information and demodulation information, comparing the RFID tag information with the demodulation information, and generating a driving signal; and a pulse oscillation module coupled to the information comparison module for receiving the driving signal, and transmitting pulse oscillating signals to the electrically erasable programmable read-only memory module, so as to allow the electrically erasable programmable read-only memory module to transmit the RFID tag information.

Abstract: A particle transporter based on travelling-wave dielectrophoresis is provided. The particle transporter includes a plurality of turn-around electrodes. The turn-around electrodes are disposed on a substrate and arranged in a fan shape. The turn-around electrodes provide an arc channel for transporting a plurality of particles. Wherein, the turn-around electrodes are not connected to each other, and neighboring sides of any two adjacent electrodes of the turn-around electrodes are approximately parallel.

Abstract: The present invention relates to a method of time-domain magnetic resonance imaging and device thereof. The method includes transiently exciting a sample; receiving a signal emitted form the sample; and processing the received signal without Fourier transformation to acquire an image. The device includes an excitation device, a detecting coil and an operating circuit to process a received emitting signal and generating an image, wherein the received emitting signal is a time-domain signal free from Fourier transformation. The time of generating an image can be reduced dramatically by the present invention.

Abstract: A detection method for preventing an automobile from colliding is applied to an automobile. The detection method includes the following steps: step (a): providing at least two detection devices, each detection device is used to measure a predetermined information of the automobile. A one-stage linear Kalman filter in each device is used to enhance the signal-to-noise ratio of the predetermined information. In step (b): utilizing the one-stage linear filter to receive the predetermined information and obtain a corrected information from the predetermined information after the signal-to-noise ratio is enhanced. In step (c): calculating the corrected information to obtain a component information having vector components of a first direction and a second direction. In step (d): enhancing the signal-to-noise ratio to enable the component information to be a contrast information. Accordingly, the convergence time of calculating the contrast information can be substantially reduced.

Abstract: A particle transporter based on travelling-wave dielectrophoresis is provided. The particle transporter includes a plurality of turn-around electrodes. The turn-around electrodes are disposed on a substrate and arranged in a fan shape. The turn-around electrodes provide an arc channel for transporting a plurality of particles. Wherein, the turn-around electrodes are not connected to each other, and neighboring sides of any two adjacent electrodes of the turn-around electrodes are approximately parallel.

Abstract: A positioning method and a positioning apparatus are provided. In this positioning method, a differential global positioning system is used to calculate a double difference of satellite distance in connection with a reference station and a receiver station. A baseline vector pointing from the reference station to the receiver station is calculated according to the double difference of satellite distance and the cosine law. The baseline vector and the position of the reference station are used to calculate the position of the receiver station. Correction coefficients are obtained according to the position of the reference station, the position of the receiver station, and the current time. The position of the receiver station is corrected according to the correction coefficients and the length of the baseline vector.

Abstract: A method of detecting a tsunami by using the global positioning system (GPS) is provided. The method includes distributing multiple GPS receivers over a sea surface in a target area, receiving signals from GPS satellites by the GPS receivers, and transmitting the signals and coordinates of the GPS receivers to a computer. The signals are then processed to acquire real-time monitoring data including the distribution of electrons in the ionosphere above the target area, and the occurrence of a tsunami is then determined based on the distribution of electrons.

Abstract: A full-wave rectifying device includes a first rectification module and a second rectification module. The first rectification module includes one or a plurality of first rectification units. The second rectification module includes one or a plurality of second rectification units. In each of a plurality of transistors, the substrate is connected to the source so as to reduce the body effect of the rectifying circuit efficiently and enable generation of a dc voltage signal through rectification by a plurality of capacitors. A multistage rectifying circuit architecture including a plurality of first rectification units and second rectification units is provided, so as to reduce the body effect of transistors of a conventional rectifier and significantly stabilize the voltage output level, thereby allowing the rectifying circuit to generate a dc voltage level of designed value.

Abstract: A dot-matrix display data refresh charging/discharging control method and system is proposed, which is designed for integration to a dot-matrix display device for providing a data refresh charging/discharging control mechanism on the dot-matrix display device. The proposed method and system is characterized by the capability of prior to a data refresh action on each pixel, switching the pixel for connection to a voltage-neutralizing point for the purpose of neutralizing the current data voltage charge on the pixel to substantially approach zero voltage level; and subsequently during the data refresh action, charging a new data voltage into the pixel. This feature allows the operation of the dot-matrix display device to have faster speed and low power consumption.

Abstract: A cascode current mirror circuit and a bandgap circuit are provided. The circuits are used together and function as a reference voltage circuit. The reference voltage circuit outputs a reference current resistant to temperature variation and ripple-voltage. Accordingly, a voltage stabilizing/regulating circuit corrects error voltage precisely and promptly, and the resultant voltage is temperature insensitive and ripple-voltage-independent.

Abstract: An LCD display design system and method are disclosed. The method includes performing operations by a variety of operation modules after initial parameters are input and an operation type is selected, so as to generate operation results and transfer the operation results to an integration module; integrating the operation results by an integration module to generate a correspondence relation such as an operation window, a compare-table or an equation, and further transferring the operation results and the correspondence relation to an output module such that the output module can display performance variations of a variety of designs corresponding to the different initial parameters. Therefore, the present invention provides a user with a convenient way to obtain optimal design parameters for designing a display pixel circuit.

Abstract: A display designing system and a method thereof. The display designing system includes a variety of operation modules and an integration module. After receiving initial parameters and selecting operation type parameters, the operation modules generate operation results and transfer the operation results to the integration module. The integration module integrates the operation results and generates a correspondence relation, such as an operation window, a compare-table and an equation. The integration module then transfers the operation results and the correspondence relation to the output module. The output module displays effect variations of a variety of designs corresponding to the initial parameters. Therefore, the method can provide a user with an easy way to obtain ideal design parameters for designing a display pixel circuit.

Abstract: The present invention relates to a dielectric resonator antenna (DRA) with bending metallic planes. The ground plane of the dielectric resonator antenna is bent around the DRA to increase the half-power beam width (HPBW) and the gain on H-plane, moreover, to improve the pattern on E-plane. The ground plane of the invention is further bent in different angles to reshape the radiation pattern of the dielectric resonator antenna, and a well is carved in the dielectric resonator antenna to increase its radiation bandwidth. The invention can also be adjusted as WiMAX sectorial antenna.

Abstract: A signal modulation device and a signal amplifier cooperative therewith. The signal modulation device includes a local oscillation signal source, a baseband signal source, a first NMOS transistor, and a second NMOS transistor, wherein the first and second NMOS transistors are coupled with the baseband signal source and form a circuit architecture of a Gilbert-cell based differential pair to be directly switched by a differential baseband signal, and a high-frequency signal from the local oscillation signal source is controlled by the baseband signal so as to generate an amplitude-modulation high-frequency signal at an output end. The single-stage signal power amplifier amplifies the amplitude-modulation signal from the preceding circuit so as to increase the magnitude of signals transmitted and simplify the preceding digital/analog signal conversion circuit in a conventional amplitude-modulation circuit.

Abstract: Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.

Abstract: The present invention relates to a circularly-polarized dielectric resonator antenna (DRA). The antenna comprises a substrate, a Wilkinson power divider, a phase shifter, a ground plane and a dielectric resonator, wherein the phase shifter is connected to the Wilkinson power divider. Besides, the dielectric resonator is disposed on the ground plane, and includes a dielectric main body and a well disposed above the substrate. Additionally, the antenna is adopted to increase the linear radiation bandwidth by utilizing the well, and transceives a circularly-polarized electromagnetic wave by utilizing the Wilkinson power divider. Consequently, the circularly-polarized dielectric resonator antenna can be applied in the fields of satellite communication, Worldwide Interoperability for Microwave Access (WiMAX), and wireless communication.

Abstract: The present invention relates to a method of time-domain magnetic resonance imaging and device thereof. The method includes transiently exciting a sample; receiving a signal emitted form the sample; and processing the received signal without Fourier transformation to acquire an image. The device includes an excitation device, a detecting coil and an operating circuit to process a received emitting signal and generating an image, wherein the received emitting signal is a time-domain signal free from Fourier transformation. The time of generating an image can be reduced dramatically by the present invention.

Abstract: Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.