Patents by Inventor Jean Jimenez

Jean Jimenez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200412124
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • Patent number: 10813367
    Abstract: The present invention provides methods of producing a fermented milk product comprising a step wherein milk is fermented, wherein: (a) the fermentation is initiated by a starter culture, which starter culture comprises lactic acid bacteria capable of metabolizing one or several carbohydrates present in the milk, (b) the fermentation is terminated by a decrease of the concentration of the one or several carbohydrates during fermentation, and (c) the decrease is at least also caused by the metabolic activity of the lactic acid bacteria. The invention further provides respective methods comprising a step, wherein at least part of the whey is separated from the fermented milk product.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 27, 2020
    Assignee: CHR. HANSEN A/S
    Inventors: Christel Garrigues, Christian Gilleladen, Mirjana Curic-Bawden, Thomas Janzen, Mimi Birkelund, Gäelle Lettier Buchhorn, Kim Ib Soerensen, Nanna Christensen, Claus Svane, Soeren Riis, Martin Bastian Pedersen, Jean-Marie Odinot, Luciana Jimenez, Pascal Lanciaux, Duncan Hamm, Choon Ming Siew
  • Patent number: 10651473
    Abstract: The present invention relates to a new lithium-doped Pernigraniline-based material, a method for the preparation thereof, its use in various applications, an electrode comprising said lithium-doped Pernigraniline-based material and its preparation method, a membrane comprising said lithium-doped Pernigraniline-based material and its preparation method, and an electrochemical storage system comprising said electrode.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: May 12, 2020
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE DE NANTES, UNIVERSITE DE PICARDIE JULES VERNE
    Inventors: Joël Gaubicher, Dominique Guyomard, Bernard Lestriez, Jean-Pierre Bonnet, Pablo Jimenez Manero
  • Publication number: 20200098743
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 10515946
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Publication number: 20190319453
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190319454
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190296007
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean JIMENEZ
  • Patent number: 10361188
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Publication number: 20180374983
    Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Dominique GOLANSKI, Jean JIMENEZ, Didier DUTARTRE, Olivier GONNARD
  • Publication number: 20180269199
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 9997512
    Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 9997907
    Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Boris Heitz, Jean Jimenez
  • Publication number: 20180130788
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Applicant: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Patent number: 9899366
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Publication number: 20170194350
    Abstract: An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.
    Type: Application
    Filed: April 25, 2016
    Publication date: July 6, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Publication number: 20170179113
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Publication number: 20170148780
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Application
    Filed: April 12, 2016
    Publication date: May 25, 2017
    Applicant: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Publication number: 20160380427
    Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.
    Type: Application
    Filed: December 10, 2015
    Publication date: December 29, 2016
    Applicant: STMicroelectronics SA
    Inventors: Johan Bourgeat, Boris Heitz, Jean Jimenez
  • Publication number: 20160315077
    Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 27, 2016
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre