Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.