Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors.

Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract: The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased.

Abstract: The electronic device comprises a first terminal and a second terminal, a buffer connected between the first terminal and the second terminal and comprising a signal input, and means for protecting against electrostatic discharges likely to occur across at least a pair of nodes of the buffer. The device comprises at least one integrated structure connected between the two nodes and said signal input, containing at least one MOS transistor and forming both said protection means and at least a part of said buffer.

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract: A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive.

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

Abstract: The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements.

Abstract: The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased.

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

Abstract: The electronic device comprises a first terminal and a second terminal, a buffer connected between the first terminal and the second terminal and comprising a signal input, and means for protecting against electrostatic discharges likely to occur across at least a pair of nodes of the buffer. The device comprises at least one integrated structure connected between the two nodes and said signal input, containing at least one MOS transistor and forming both said protection means and at least a part of said buffer.

Abstract: A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive.