Abstract: A process for exposing at least one region of a face, known as the front face, of an electronic device, the process including the following steps: A bonding step for a cover (600) to the front face, the bonding being undertaken such that the cover (600) forms a closed cavity (650) with the region, advantageously hermetically sealed; Formation of an encapsulation coating (700), of thickness E1, covering the front face and the cover (600); A thinning step for the encapsulation coating (700), the thinning step including removal of a removal thickness E2, less than the thickness E1, of the encapsulation coating (700), the removal thickness E2 being adjusted such that an opening is formed in the cover (600).

Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.

Abstract: A packaging structure including at least one hermetically sealed cavity in which at least one microelectronic device is arranged, the cavity being formed between a substrate and at least one cap layer through which several release holes are formed. Several separated portions of metallic material are provided such that each of the separated portions of metallic material is arranged on the cap layer above and around one of the release holes and forms an individual and hermetical plug of said one of the release holes. At least one diffusion barrier layer including at least one non-metallic material is arranged on the cap layer and forms a diffusion barrier against an atmosphere outside the cavity at least around the release holes. Parts of the diffusion barrier layer are not covered by the portions of metallic material.

Abstract: A process for exposing at least one region of a face, known as the front face, of an electronic device, the process including the following steps: A bonding step for a cover (600) to the front face, the bonding being undertaken such that the cover (600) forms a closed cavity (650) with the region, advantageously hermetically sealed ; Formation of an encapsulation coating (700), of thickness E1, covering the front face and the cover (600); A thinning step for the encapsulation coating (700), the thinning step including removal of a removal thickness E2, less than the thickness E1, of the encapsulation coating (700), the removal thickness E2 being adjusted such that an opening is formed in the cover (600).

Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.

Abstract: Method for encapsulating a microelectronic device, comprising the following steps: producing a sacrificial portion covering the device; producing a cover covering the sacrificial portion, comprising two superimposed layers of separate materials and having different residual stresses and/or coefficients of thermal expansion; etching, through the cover, of a trench of which the pattern comprises a curve and/or two straight non-parallel segments; etching of the sacrificial portion through the trench; depositing a sealing material on the trench; in which, during the etching of the sacrificial portion, a portion of the cover defined by the trench deforms under the effect of a mechanical stress generated by the residual stresses and/or a thermal expansion of the layers of the cover and increases the dimensions of the trench, this stress being eliminated before the sealing of the trench.

Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.

Abstract: Method for encapsulating a microelectronic device, comprising the following steps: producing a sacrificial portion covering the device; producing a cover covering the sacrificial portion, comprising two superimposed layers of separate materials and having different residual stresses and/or coefficients of thermal expansion; etching, through the cover, of a trench of which the pattern comprises a curve and/or two straight non-parallel segments; etching of the sacrificial portion through the trench; depositing a sealing material on the trench; in which, during the etching of the sacrificial portion, a portion of the cover defined by the trench deforms under the effect of a mechanical stress generated by the residual stresses and/or a thermal expansion of the layers of the cover and increases the dimensions of the trench, this stress being eliminated before the sealing of the trench.

Abstract: The present invention concerns a microelectronic package (1) comprising a microelectronic structure (2) having at least a first opening (3) and defining a first cavity (4), a capping layer (9) having at least a second opening (10) and defining a second cavity (11) which is connected to the first cavity (4), wherein the capping layer (9) is arranged over the microelectronic structure (2) such that the second opening (10) is arranged over the first opening (3), and a sealing layer (13) covering the second opening (10), thereby sealing the first cavity (4) and the second cavity (11). Moreover, the present invention concerns a method of manufacturing the microelectronic package (1).

Abstract: A packaging structure including at least one hermetically sealed cavity in which at least one microelectronic device is arranged, the cavity being formed between a substrate and at least one cap layer through which several release holes are formed; several separated portions of metallic material such that each of the separated portions of metallic material is arranged on the cap layer above and around one of the release holes and forms an individual and hermetical plug of said one of the release holes; at least one diffusion barrier layer comprising at least one non-metallic material, arranged on the cap layer and forming a diffusion barrier against an atmosphere outside the cavity at least around the release holes; and wherein parts of the diffusion barrier layer are not covered by the portions of metallic material.

Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.

Abstract: A method of encapsulating a microelectronic device arranged on a substrate, comprising at least the following steps: a) formation of a portion of sacrificial material covering at least one part of the microelectronic device, the volume of which occupies a space intended to form at least one part of a cavity in which the device is intended to be encapsulated; b) deposition of a layer based on at least one getter material, covering at least one part of the portion of sacrificial material; c) formation of at least one orifice through at least the layer of getter material, forming an access to the portion of sacrificial material; d) elimination of the portion of sacrificial material via the orifice, forming the cavity in which the microelectronic device is encapsulated; and e) sealing of the cavity.

Abstract: Method of hermetically sealing a hole with a fuse material, comprising the following steps: applying a portion of wettable material onto a surface such that it completely surrounds the hole made through said surface and is located outside the hole, or completely surrounds a first part of said surface corresponding to a location of the hole; applying a portion of fuse material on the portion of wettable material and on a second part of said surface located around the portion of wettable material; reflowing the portion of fuse material to form a bump of fuse material which has a shape corresponding to a part of a sphere, which is fastened only to the portion of wettable material and which hermetically plugs the hole; wherein the hole is made in said surface before reflowing the portion of fuse material.

Abstract: Method of hermetically sealing a hole with a fuse material, comprising the following steps: applying a portion of wettable material onto a surface such that it completely surrounds the hole made through said surface and is located outside the hole, or completely surrounds a first part of said surface corresponding to a location of the hole; applying a portion of fuse material on the portion of wettable material and on a second part of said surface located around the portion of wettable material; reflowing the portion of fuse material to form a bump of fuse material which has a shape corresponding to a part of a sphere, which is fastened only to the portion of wettable material and which hermetically plugs the hole; wherein the hole is made in said surface before reflowing the portion of fuse material.

Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.

Abstract: A process for making an encapsulation structure comprising the following steps: 1) make at least one portion of material capable of releasing at least one gas when said material is heated, the portion of material communicating with the inside of a hermetically closed cavity of the encapsulation structure, 2) heat all or part of said portion of material such that at least part of the gas is released from said portion of material in the cavity, and in which said portion of material capable of releasing at least one gas when said material is heated comprises elements trapped in said portion of material, said trapped elements being released from said portion of material in gaseous form when said material is heated.

Abstract: An encapsulation structure including at least one hermetically sealed cavity in which a device, an electronic component produced on a first substrate, and a getter material layer covering the electronic component in order to block the gases capable of being degassed by the electronic component, are enclosed. A top surface of the device is free of contact with the getter material layer.

Abstract: A method for producing a sealed cavity, including: a) producing a sacrificial layer on a substrate; b) producing a cover layer covering at least the sacrificial layer and a portion of the face of the substrate not covered by the sacrificial layer, the cover layer including lateral flanks forming, with the substrate, an angle of less than 90°; c) producing a hole through one of the lateral flanks of the cover layer such that a maximum distance between the substrate and an edge of the hole is less than approximately 3 ?m, the hole crossing a portion of the cover layer deposited on a portion of the substrate not covered by the sacrificial layer; d) eliminating the sacrificial layer through the hole, forming the cavity; and e) depositing at least one material plugging the hole in a sealed fashion.

Abstract: A structure for encapsulating at least one electronic device, including at least one first cavity bounded by a support and at least one cap provided on the support and wherein the electronic device is encapsulated, at least one aperture passing through the cap and communicating the inside of the first cavity with at least one portion of getter material provided in at least one second cavity which is arranged on the support and adjacent to the first cavity, at least one part of said portion of getter material being provided on the support or against at least one outer side wall of the first cavity, the first cavity and the second cavity forming together a hermetically sealed volume.

Abstract: A process for making an encapsulation structure comprising the following steps: make at least one portion of material capable of releasing at least one gas when said material is heated, the portion of material communicating with the inside of a hermetically closed cavity of the encapsulation structure, heat all or part of said portion of material such that at least part of the gas is released from said portion of material in the cavity, and in which said portion of material capable of releasing at least one gas when said material is heated comprises elements trapped in said portion of material, said trapped elements being released from said portion of material in gaseous form when said material is heated.