Patents by Inventor Jean-Luc Danger
Jean-Luc Danger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11336468Abstract: A circuit for a Synthetic Physically Unclonable Function, acronym SPUF, in a computer device, wherein the circuit is configured to receive data from a plurality of hardware sensors and/or actuators accessible in the computer device; to determine deviations in the data; to determine a multivariate distribution of the deviations and to determine an identifier from the multivariate distribution. In described developments, deviations comprise random errors, statistical moments in data originating from sensors and/or actuators amongst accessible ones in the computer device can be selected, and entropy can be maximized. Computer program product embodiments are described.Type: GrantFiled: December 20, 2017Date of Patent: May 17, 2022Assignee: SECURE-IC SASInventors: Philippe Nguyen, Robert Nguyen, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger, Adrien Facon
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Publication number: 20220138527Abstract: Process and system for processing data by an artificial neural network comprising several pooling or convolutional layers all associated with neural matrices, including for each layer of the several successive layers obtaining a reordered matrix, obtaining a division of the reordered matrix into a plurality of contiguous submatrices having given widths and heights, and grouping execution of the individual operations to be performed for each submatrix.Type: ApplicationFiled: November 5, 2021Publication date: May 5, 2022Inventors: Hervé CHABANNE, Linda GUIGA, Jean-Luc DANGER
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Patent number: 11038680Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge.Type: GrantFiled: December 21, 2017Date of Patent: June 15, 2021Assignee: SECURE-IC SASInventors: Jean-Luc Danger, Philippe Nguyen
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Patent number: 11005668Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system further comprises: A helper data generator (2) configured to generate a helper data comprising a set of bits, a bit of the helper data being generated in association with each applied challenge, the helper data generator being configured to generate each helper data bit from the physical variable difference provided by the PUF in response to the application of the associated challenge, the system further comprising a secret information generator (3) for extracting secret information from the helper data.Type: GrantFiled: December 21, 2017Date of Patent: May 11, 2021Inventors: Jean-Luc Danger, Philippe Nguyen
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Patent number: 10855476Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.Type: GrantFiled: July 1, 2016Date of Patent: December 1, 2020Assignee: SECURE-IC SASInventors: Rachid Dafali, Jean-Luc Danger, Sylvain Guilley, Florent Lozac'h
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Patent number: 10776484Abstract: Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented.Type: GrantFiled: January 12, 2016Date of Patent: September 15, 2020Assignees: NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY, TELECOM PARISTECHInventors: Makoto Nagata, Jean-Luc Danger, Daisuke Fujimoto, Shivam Bhasin
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Publication number: 20200195417Abstract: A cryptography circuit, protected notably against information-leak observation attacks is provided. The cryptography circuit comprises a functional key kc for executing a cryptography algorithm. It comprises a second key ki unique and specific to the circuit making it possible to protect by masking the functional and confidential key kc or a confidential implementation of the algorithm.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Jean-Luc DANGER, Sylvain GUILLEY
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Patent number: 10630492Abstract: There is provided a method for testing a Physically Unclonable Function (PUF) implemented in a device, said PUF being configured to receive at least one challenge, each challenge comprising a set of bits, and to produce a set of responses, each response comprising at least one bit and corresponding to one challenge, said PUF comprising a circuitry including a set of PUF elements, each PUF element being controlled by at least one input bit corresponding to at least one bit of said challenge, wherein the method comprises the steps of: applying at least one bit of the challenge to the PUF instance; determining (300) identifiers for at least some of the PUF elements, the identifier of each PUF element being determined from the response output by said PUF element in response to said at least one bit of the challenge; applying a statistical randomness test (304) to a group of identifiers comprising at least some of the identifiers determined for said PUF elements, which provides a test indicator; and testing saiType: GrantFiled: April 6, 2017Date of Patent: April 21, 2020Assignee: SECURE-IC SASInventors: Sylvain Guilley, Jean-Luc Danger, Philippe Nguyen
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Patent number: 10607006Abstract: There is disclosed a system for monitoring the security of a target system (110) with a circuit (120), the target system (110) comprising at least one processor (111) and wherein: the circuit (120) comprises a finite-state machine (122) configured to receive data from one or more sensors (130) distributed in the target system (110), at least one sensor (1303) being located on the processor (111) of the target system (110); the finite-state machine (122) is configured to determine a state output in response to data received from sensors (130); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.Type: GrantFiled: July 27, 2017Date of Patent: March 31, 2020Assignee: SECURE-IC SASInventors: Jean-Luc Danger, Sylvain Guilley, Thibault Porteboeuf
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Publication number: 20200092116Abstract: A circuit for a Synthetic Physically Unclonable Function, acronym SPUF, in a computer device, wherein the circuit is configured to receive data from a plurality of hardware sensors and/or actuators accessible in the computer device; to determine deviations in the data; to determine a multivariate distribution of the deviations and to determine an identifier from the multivariate distribution. In described developments, deviations comprise random errors, statistical moments in data originating from sensors and/or actuators amongst accessible ones in the computer device can be selected, and entropy can be maximized. Computer program product embodiments are described.Type: ApplicationFiled: December 20, 2017Publication date: March 19, 2020Inventors: Philippe NGUYEN, Robert NGUYEN, Youssef SOUISSI, Sylvain GUILLEY, Jean-Luc DANGER, Adrien FACON
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Patent number: 10331912Abstract: The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in: selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria, constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order, determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2k, where k designates the number of bits representing said variable x; substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that: any operation of writing on the variable xType: GrantFiled: July 30, 2015Date of Patent: June 25, 2019Assignee: SECURE-IC SASInventors: Sylvain Guilley, Thibaut Porteboeuf, Jean-Luc Danger
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Patent number: 10236262Abstract: Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102) having a front surface (20) and a back surface (21), the IC device further comprising a front side part (101) arranged on the front surface of the substrate (102) and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (13). The system comprises an internal shield (12) arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.Type: GrantFiled: December 28, 2016Date of Patent: March 19, 2019Inventors: Sylvain Guilley, Thibault Porteboeuf, Jean-Luc Danger
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Publication number: 20180183613Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.Type: ApplicationFiled: July 1, 2016Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Rachid DAFALI, Jean-Luc DANGER, Sylvain GUILLEY, Florent LOZAC?H
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Publication number: 20180183614Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system further comprises: A helper data generator (2) configured to generate a helper data comprising a set of bits, a bit of the helper data being generated in association with each applied challenge, the helper data generator being configured to generate each helper data bit from the physical variable difference provided by the PUF in response to the application of the associated challenge, the system further comprising a secret information generator (3) for extracting secret information from the helper data.Type: ApplicationFiled: December 21, 2017Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Philippe NGUYEN
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Publication number: 20180183589Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge.Type: ApplicationFiled: December 21, 2017Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Philippe NGUYEN
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Publication number: 20180032723Abstract: There is disclosed a system for monitoring the security of a target system (110) with a circuit (120), the target system (110) comprising at least one processor (111) and wherein: the circuit (120) comprises a finite-state machine (122) configured to receive data from one or more sensors (130) distributed in the target system (110), at least one sensor (1303) being located on the processor (111) of the target system (110); the finite-state machine (122) is configured to determine a state output in response to data received from sensors (130); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.Type: ApplicationFiled: July 27, 2017Publication date: February 1, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Sylvain GUILLEY, Thibault PORTEBOEUF
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Publication number: 20180004944Abstract: Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented.Type: ApplicationFiled: January 12, 2016Publication date: January 4, 2018Inventors: Makoto NAGATA, Jean-Luc DANGER, Daisuke FUJIMOTO, Shivam BHASIN
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Publication number: 20170295026Abstract: There is provided a method for testing a Physically Unclonable Function (PUF) implemented in a device, said PUF being configured to receive at least one challenge, each challenge comprising a set of bits, and to produce a set of responses, each response comprising at least one bit and corresponding to one challenge, said PUF comprising a circuitry including a set of PUF elements, each PUF element being controlled by at least one input bit corresponding to at least one bit of said challenge, wherein the method comprises the steps of: applying at least one bit of the challenge to the PUF instance; determining (300) identifiers for at least some of the PUF elements, the identifier of each PUF element being determined from the response output by said PUF element in response to said at least one bit of the challenge; applying a statistical randomness test (304) to a group of identifiers comprising at least some of the identifiers determined for said PUF elements, which provides a test indicator; and testing saiType: ApplicationFiled: April 6, 2017Publication date: October 12, 2017Applicant: SECURE-IC SASInventors: Sylvain GUILLEY, Jean-Luc DANGER
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Publication number: 20170228562Abstract: The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in: selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria, constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order, determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2k, where k designates the number of bits representing said variable x; substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that: any operation of writing on the variable xType: ApplicationFiled: July 30, 2015Publication date: August 10, 2017Applicant: SECURE-IC SASInventors: Sylvain GUILLEY, Thibaut PORTEBOEUF, Jean-Luc DANGER
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Publication number: 20170186706Abstract: Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102) having a front surface (20) and a back surface (21), the IC device further comprising a front side part (101) arranged on the front surface of the substrate (102) and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (13). The system comprises an internal shield (12) arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.Type: ApplicationFiled: December 28, 2016Publication date: June 29, 2017Applicant: SECURE-IC SASInventors: Sylvain GUILLEY, Thibault PORTEBOEUF, Jean-Luc DANGER