Abstract: The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test.

Abstract: A cryptography circuit protected by masking, said circuit including means for encrypting binary words using at least one key krc, means for applying linear processing operations and nonlinear processing operations to said words and means for masking said words. The binary words are unmasked upstream of the nonlinear processing operations by using a mask kri and masked downstream of said processing operations by using a mask kr+1i, the masks kri and kr+1i being chosen from a set of masks that is specific to each instance of the circuit.

Abstract: In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.

Abstract: A method and apparatus are provided for sending pulses from a sender device to a receiver device in a transmission channel. The pulses represent information symbols, with each of these pulses being associated with a time slot in a symbol time. The method includes a training step that is carried out before sending payload information and that includes sending a training sequence made up of two parts. A first part of the training sequence includes at least one pulse of energy that is greater than the energy of a pulse carrying payload information. There are a large number of time slots between the sending of the pulse and the sending of the next pulse. A second part of the training sequence includes a set of pulses known in advance and similar to the pulses used for carrying payload information, the energy of each of these pulses being equivalent to the energy of a pulse carrying payload information.

Abstract: A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.

Abstract: A silicon integrated circuit includes a physically non-copyable function LPUF that generates a signature specific to the circuit. The function includes a ring oscillator composed of a loop traversed by a signal. The loop is formed of N topologically identical chains of lags connected in series and an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also includes a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after updating the control words, and the control module can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided.

Abstract: A cryptography circuit protected against observation attacks comprises at least one register R providing a variable x masked by the mask m, the masked variable being encrypted by a first substitution box S -in a cyclic manner. The circuit also comprises a mask register M delivering at each cycle a mask mt, the transformation of m, the mask m being extracted from mt before being encrypted by a second substitution box S?, the new mask m? obtained on output from this box S? is transformed into a mask m?t before being stored in the mask register M. The transformation consists of a bijection or a composition law making it possible to reduce or indeed to cancel any high-order attack in accordance with a model of activity of the registers R and M. Cryptography circuits are protected against high-order observation attacks on installations based on masking.

Abstract: A silicon integrated circuit comprises a physically non-copyable function LPUF allowing the generation of a signature specific to said circuit. Said function comprises a ring oscillator composed of a loop traversed by a signal, being formed of N topologically identical chains of lags, connected in series and of an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also comprises a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after the updating of the control words, and means can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided.

Abstract: A cryptography circuit protected by masking, said circuit including means for encrypting binary words using at least one key krc, means for applying linear processing operations and nonlinear processing operations to said words and means for masking said words. The binary words are unmasked upstream of the nonlinear processing operations by using a mask kri and masked downstream of said processing operations by using a mask kr+1i, the masks kri and kr+1i being chosen from a set of masks that is specific to each instance of the circuit.

Abstract: A cryptography circuit protected against observation attacks comprises at least one register R providing a variable x masked by the mask m, the masked variable being encrypted by a first substitution box S in a cyclic manner. The circuit also comprises a mask register M delivering at each cycle a mask mt, the transformation of m, the mask m being extracted from mt before being encrypted by a second substitution box S?, the new mask m? obtained on output from this box S? is transformed into a mask m?t before being stored in the mask register M. The transformation consists of a bijection or a composition law making it possible to reduce or indeed to cancel any high-order attack in accordance with a model of activity of the registers R and M. Cryptography circuits are protected against high-order observation attacks on installations based on masking.

Abstract: In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.

Abstract: A cryptography circuit, protected notably against information-leak observation attacks, comprises a functional key kc for executing a cryptography algorithm. It comprises a second key ki unique and specific to the circuit making it possible to protect by masking the functional and confidential key kc or a confidential implementation of the algorithm.

Abstract: The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test.

Abstract: A method for protecting a programmable logic circuit includes storing data file(s) used for the configuration of the programmable resources of the circuit in a non-volatile memory after having been encrypted. A decryption module internal to the circuit is responsible for decrypting the file(s) by using a secret key stored in the circuit, the decryption module being protected against attacks aiming to obtain the key during the decryption operation by implementing at least one countermeasure technique.

Abstract: A method and apparatus are provided for sending pulses from a sender device to a receiver device in a transmission channel. The pulses represent information symbols, with each of these pulses being associated with a time slot in a symbol time. The method includes a training step that is carried out before sending payload information and that includes sending a training sequence made up of two parts. A first part of the training sequence includes at least one pulse of energy that is greater than the energy of a pulse carrying payload information. There are a large number of time slots between the sending of the pulse and the sending of the next pulse. A second part of the training sequence includes a set of pulses known in advance and similar to the pulses used for carrying payload information, the energy of each of these pulses being equivalent to the energy of a pulse carrying payload information.

Abstract: A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.

Abstract: Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.

Abstract: Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.

Abstract: A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.

Abstract: A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.