Patents by Inventor Jean-Michel Caia

Jean-Michel Caia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9787431
    Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 10, 2017
    Assignee: INPHI CORPORATION
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi
  • Patent number: 9647761
    Abstract: Flexible rate communication signalling apparatus and methods are disclosed. A determination is made as to a set of one or more of first frames and second frames which would provide a desired communication rate. The first frames and the second frames have a common frame structure but different associated rates. The determined set of one or more of the first frames and the second frames, including received client signals, is generated.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 9, 2017
    Assignee: INPHI CORPORATION
    Inventors: Jean-Michel Caia, Juan-Carlos Calderon, Arun Zarabi
  • Publication number: 20160344512
    Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi
  • Patent number: 9461764
    Abstract: Provided is an apparatus and method for transmitting data over a communication channel having at least one physical lane for transmitting data. The apparatus includes, for each physical lane, allocation circuitry configured for allocating data in logical lanes corresponding to the physical lane. The apparatus also includes, for each physical lane, a multiplexer configured for bit-interleaving the data from the logical lanes corresponding to the physical lane into interleaved data for transmission over the physical lane. In accordance with an embodiment of the present disclosure, for each physical lane, the allocation circuitry is configured for allocating the data such that the interleaved data for transmission over the physical lane has clusters of sequential bits of the same symbol. Thus, upon transmission and reception by a receiver, any correlated errors affecting sequential bits may affect fewer symbols. Also provided is an apparatus and method for receiving data in a complementary manner.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 4, 2016
    Assignee: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi, Michael Miller
  • Patent number: 9438376
    Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Cortina Systems, Inc.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi
  • Patent number: 9252903
    Abstract: Despite a recent revision, IEEE 1588™-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 2, 2016
    Assignee: Cortina Systems, Inc.
    Inventors: Jasson Flinn, Juan-Carlos Calderon, Jean-Michel Caia, Arun Zarabi, Scott Feller
  • Publication number: 20150003827
    Abstract: Provided is an apparatus and method for transmitting data over a communication channel having at least one physical lane for transmitting data. The apparatus includes, for each physical lane, allocation circuitry configured for allocating data in logical lanes corresponding to the physical lane. The apparatus also includes, for each physical lane, a multiplexer configured for bit-interleaving the data from the logical lanes corresponding to the physical lane into interleaved data for transmission over the physical lane. In accordance with an embodiment of the present disclosure, for each physical lane, the allocation circuitry is configured for allocating the data such that the interleaved data for transmission over the physical lane has clusters of sequential bits of the same symbol. Thus, upon transmission and reception by a receiver, any correlated errors affecting sequential bits may affect fewer symbols. Also provided is an apparatus and method for receiving data in a complementary manner.
    Type: Application
    Filed: June 3, 2014
    Publication date: January 1, 2015
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi, Michael Miller
  • Patent number: 8862797
    Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: October 14, 2014
    Assignee: Cortina Systems, Inc.
    Inventors: Dennis Albert Doidge, Juan-Carlos Calderon, Jean-Michel Caia
  • Publication number: 20140270780
    Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi
  • Publication number: 20140164546
    Abstract: There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.
    Type: Application
    Filed: October 18, 2011
    Publication date: June 12, 2014
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Dennis Albert DOIDGE, Juan-Carlos CALDERON, Jean-Michel CAIA
  • Patent number: 8494363
    Abstract: Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: July 23, 2013
    Assignee: Cortina Systems, Inc.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arun Zarabi, Aws Shallal, Theron Paul Niederer
  • Publication number: 20130100832
    Abstract: Despite a recent revision, IEEE 1588™-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Jasson Flinn, Juan-Carlos Calderon, Jean-Michel Caia, Arun Zarabi, Scott Feller
  • Patent number: 8392788
    Abstract: A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 5, 2013
    Assignee: Cortina Systems, Inc.
    Inventors: Juan-Carlos Calderon, Arun Zarabi, Jean-Michel Caia
  • Publication number: 20120269511
    Abstract: Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arun Zarabi, Aws Shallal, Theron Paul Niederer
  • Publication number: 20110126074
    Abstract: A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 26, 2011
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Arun Zarabi, Jean-Michel Caia
  • Patent number: 7656891
    Abstract: A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Soowan Suh, Jing Ling, Jean-Michel Caia, Alejandro Lenero Beracoechea
  • Patent number: 7583599
    Abstract: A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Jing Ling, Vasan Karighattam, Jean-Michel Caia, Edward Pullin, Mark Feuerstraeter, Juan-Carlos Calderon
  • Patent number: 7564777
    Abstract: In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Patent number: 7525977
    Abstract: A device for mapping and demapping cells in an orderly manner is provided. The device employs a channel identifier and in certain configurations a buffer and series of stages to provide for relatively ordered, predictable mapping and demapping of data, such as virtual concatenation data.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Eduard Lecha, Vasan Karighattam, Steve J. Clohset, Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Patent number: RE45248
    Abstract: A method and system for interconnecting multiple distributed components in a communication network is provided. The design includes a multiple order cross connection fabric employed to interconnect multiple orders of data with at least one distributed component in the communication network. The design may further include at least one order of path termination and adaptation connection, where the at least one order of path termination and adaptation connection providing an interface between the multiple order cross connection fabric and a data management system. The design may be implemented in a SONET/SDH environment.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Michael Ho, Miriam Qunell, Jean-Michel Caia