Patents by Inventor Jean-Michel Daga
Jean-Michel Daga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8576631Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.Type: GrantFiled: March 1, 2011Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventor: Jean-Michel Daga
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Patent number: 8416636Abstract: Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns.Type: GrantFiled: December 29, 2010Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Eric S. Carman, Philippe Bruno Bauser, Jean-Michel Daga
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Patent number: 8214729Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.Type: GrantFiled: December 22, 2011Date of Patent: July 3, 2012Assignee: Atmel Rousset S.A.S.Inventors: Godard Benoit, Jean Michel Daga
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Patent number: 8199595Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.Type: GrantFiled: September 7, 2010Date of Patent: June 12, 2012Assignee: Micron Technology, Inc.Inventors: Philippe Bruno Bauser, Jean-Michel Daga
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Publication number: 20120096334Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.Type: ApplicationFiled: December 22, 2011Publication date: April 19, 2012Applicant: ATMEL CORPORATIONInventors: Benoit Godard, Jean Michel Daga
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Patent number: 8112699Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.Type: GrantFiled: February 14, 2008Date of Patent: February 7, 2012Assignee: Atmel Rousset S.A.S.Inventors: Benoit Godard, Jean Michel Daga
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Publication number: 20110216617Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.Type: ApplicationFiled: March 1, 2011Publication date: September 8, 2011Applicant: Innovative Silicon ISi SAInventor: Jean-Michel Daga
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Publication number: 20110199848Abstract: Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns.Type: ApplicationFiled: December 29, 2010Publication date: August 18, 2011Applicant: Innovative Silicon ISi SAInventors: Eric Carman, Philippe Bruno Bauser, Jean-Michel Daga
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Publication number: 20110058436Abstract: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Applicant: Innovative Silicon ISi SAInventors: Philippe Bruno BAUSER, Jean-Michel Daga
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Publication number: 20100127752Abstract: A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs.Type: ApplicationFiled: November 24, 2008Publication date: May 27, 2010Applicant: ATMEL CorporationInventors: Jimmy Fort, Michel Cuenca, Emmanuel Racape, Jean-Michel Daga
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Publication number: 20090210774Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: ATMEL CORPORATIONInventors: Benoit Godard, Jean Michel Daga
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Patent number: 7567448Abstract: A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes a FLOating gate Tunnel OXide (FLOTOX) element. The FLOTOX element includes a single floating gate transistor and a high voltage select transistor and can store at least a portion of a data word. Each CAM cell also preferably includes at least one low voltage transistor capable of comparing the portion of data word stored in the FLOTOX element with the portion of searched word. The search line(s) provide search word(s). The comparator(s) are connected with the search line(s) and the memory cells. The comparator(s) compare the data word stored by the portion of the plurality of memory cells and the search word. The match line(s) indicate whether the search word matches the data word stored by the portion of the plurality of memory cells.Type: GrantFiled: January 5, 2007Date of Patent: July 28, 2009Assignee: Atmel CorporationInventors: Benoit Godard, Olivier Ginez, Jean Michel Daga
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Patent number: 7450429Abstract: A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high voltage level, and to select one of the voltage levels. A memory array, with a word line and a bit line, is configured to receive the external and high voltage levels at the word line and the high voltage levels at the bit line. A word line driver is configured to provide the external and high voltage levels to the word line. A bit line selector is configured to select the bit line and receive the high, external, and regulated voltage levels. A bit line driver is configured to provide the external voltage levels to the bit line selector.Type: GrantFiled: October 6, 2006Date of Patent: November 11, 2008Assignee: Atmel CorporationInventor: Jean-Michel Daga
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Publication number: 20080165557Abstract: A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes a FLOating gate Tunnel OXide (FLOTOX) element. The FLOTOX element includes a single floating gate transistor and a high voltage select transistor and can store at least a portion of a data word. Each CAM cell also preferably includes at least one low voltage transistor capable of comparing the portion of data word stored in the FLOTOX element with the portion of searched word. The search line(s) provide search word(s). The comparator(s) are connected with the search line(s) and the memory cells. The comparator(s) compare the data word stored by the portion of the plurality of memory cells and the search word. The match line(s) indicate whether the search word matches the data word stored by the portion of the plurality of memory cells.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Inventors: Benoit Godard, Olivier Ginez, Jean Michel Daga
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Patent number: 7365585Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.Type: GrantFiled: August 9, 2006Date of Patent: April 29, 2008Assignee: Atmel CorporationInventors: Jimmy Fort, Jean-Michel Daga
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Patent number: 7352640Abstract: A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node.Type: GrantFiled: August 9, 2006Date of Patent: April 1, 2008Assignee: Atmel CorporationInventors: Jimmy Fort, Jean-Michel Daga
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Publication number: 20080042731Abstract: A charge pump circuit having a first voltage node acting as an input when the charge pump circuit boosts negative voltages, and acting as an output when the charge pump circuit boosts positive voltages and a second voltage node acting as an input when the charge pump circuit boosts positive voltages, and acting as an output when the charge pump circuit boosts negative voltages. The charge pump circuit further has a first pump capacitor, a second pump capacitor, a first auxiliary capacitor, and a second auxiliary capacitor.Type: ApplicationFiled: October 29, 2007Publication date: February 21, 2008Applicant: ATMEL CORPORATIONInventors: Jean-Michel Daga, Emmanuel Racape
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Publication number: 20080036516Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.Type: ApplicationFiled: August 9, 2006Publication date: February 14, 2008Applicant: Atmel CorporationInventors: Jimmy Fort, Jean-Michel Daga
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Publication number: 20080037345Abstract: A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node.Type: ApplicationFiled: August 9, 2006Publication date: February 14, 2008Applicant: ATMEL CORPORATIONInventors: Jimmy Fort, Jean-Michel Daga
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Patent number: 7330375Abstract: A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, and a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline. To sense multiple current levels and multiple stored bits per memory cell, multiple direct current amplification circuits are electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, multiple current-to-voltage conversion circuits for converting a sensed current to a voltage, and a multiple voltage amplification or inverter circuits for amplifying the voltage and detecting a multitude of current levels. The multitude of current levels are converted or decoded into multiple bits. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.Type: GrantFiled: August 15, 2005Date of Patent: February 12, 2008Assignee: Atmel CorporationInventors: Jean-Michel Daga, Caroline Papaix