Patents by Inventor Jean-Oliver Plouchart

Jean-Oliver Plouchart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8350737
    Abstract: A flash analog to digital converter and a method and system for dynamically calibrating the flash analog to digital converter. The analog to digital converter may include a track and hold circuit and a plurality of comparators. The analog to digital converter may also include an under-sampling circuit configured to convert a digitized reference signal into an under-sampled digitized reference signal with a frequency of the calibration frequency divided by a positive number M. The under-sampling circuit may be further configured to calibrate a subsequent signal based on the under-sampled digitized reference signal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mihai A. T. Sanduleanu, Jean-Oliver Plouchart
  • Publication number: 20120176259
    Abstract: A flash analog to digital converter and a method and system for dynamically calibrating the flash analog to digital converter. The analog to digital converter may include a track and hold circuit and a plurality of comparators. The analog to digital converter may also include an under-sampling circuit configured to convert a digitized reference signal into an under-sampled digitized reference signal with a frequency of the calibration frequency divided by a positive number M. The under-sampling circuit may be further configured to calibrate a subsequent signal based on the under-sampled digitized reference signal.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Mihai A. T. Sanduleanu, Jean-Oliver Plouchart
  • Publication number: 20120108210
    Abstract: A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Oliver Plouchart
  • Patent number: 8121620
    Abstract: A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Oliver Plouchart
  • Patent number: 8039354
    Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
  • Patent number: 7816197
    Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Oliver Plouchart, Robert E. Trzcinski
  • Patent number: 7768055
    Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
  • Patent number: 7689946
    Abstract: A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonghae Kim, Sungjae Lee, Jean-Oliver Plouchart, Scott Keith Springer
  • Publication number: 20090213522
    Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
    Type: Application
    Filed: May 8, 2009
    Publication date: August 27, 2009
    Applicant: International Business Machines Corporation
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Oliver Plouchart, Robert E. Trzcinski
  • Publication number: 20080231499
    Abstract: A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Oliver Plouchart
  • Publication number: 20080109770
    Abstract: A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
    Type: Application
    Filed: October 19, 2006
    Publication date: May 8, 2008
    Inventors: Jonghae Kim, Sungjae Lee, Jean-Oliver Plouchart, Scott Keith Springer
  • Patent number: 7139990
    Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence F. Wagner, Jr., Mohamed Talbi, John M. Safran, Kun Wu
  • Publication number: 20050216873
    Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
    Type: Application
    Filed: March 23, 2004
    Publication date: September 29, 2005
    Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence Wagner, Mohamed Talbi, John Safran, Kun Wu