Patents by Inventor Jean Olivier

Jean Olivier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10033081
    Abstract: Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Duixian Liu, Jean-Olivier Plouchart, Alberto Valdes-Garcia
  • Patent number: 10026752
    Abstract: An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral bipolar junction transistors include a plurality of monolithic emitter-collector regions coplanar to each other. Each of the emitter-collector regions is both an emitter region of a first bipolar junction transistor a collector region of a second bipolar junction transistor from the lateral bipolar junction transistors. Accordingly, the lateral bipolar junction transistors are electrically coupled in series circuit at the emitter-collector regions.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alberto Valdes Garcia, Tak H. Ning, Jean-Olivier Plouchart, Ghavam G. Shahidi, Jeng-Bang Yau
  • Patent number: 10025029
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10007057
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10001598
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9977185
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 22, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Publication number: 20180114785
    Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 26, 2018
    Inventors: Russell A. Budd, Mounir Meghelli, Jason Scott Orcutt, Jean-Olivier Plouchart
  • Patent number: 9935088
    Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Mounir Meghelli, Jason Scott Orcutt, Jean-Olivier Plouchart
  • Patent number: 9935089
    Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Mounir Meghelli, Jason Scott Orcutt, Jean-Olivier Plouchart
  • Publication number: 20180069803
    Abstract: Processes pending execution in respective compute nodes (N1-Nn) of a cluster of a distributed HPC computer can communicate with one another by message exchange through an interconnected fabric. To exchange messages between the processes a method is proposed to identify the physical cards associated with the compute nodes directly from the hostname of the compute nodes as they are used in the user program. This direct identification is made from at least one mapping table (MT1) associating bijectively the hostname of each compute node of the cluster with the unique logical address of the associated physical card. This mapping table is kept in a component of the computer responsible for managing the fabric, i.e. the fabric manager (FM1). Various implementations enable scaling when accomplishing the method of message exchange between processes.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 8, 2018
    Inventors: Guillaume PAPAURE, Jean-Vincent FICET, Jean-Olivier GERPHAGNON
  • Publication number: 20180061853
    Abstract: An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral bipolar junction transistors include a plurality of monolithic emitter-collector regions coplanar to each other. Each of the emitter-collector regions is both an emitter region of a first bipolar junction transistor a collector region of a second bipolar junction transistor from the lateral bipolar junction transistors. Accordingly, the lateral bipolar junction transistors are electrically coupled in series circuit at the emitter-collector regions.
    Type: Application
    Filed: August 28, 2016
    Publication date: March 1, 2018
    Inventors: Alberto Valdes Garcia, Tak H. Ning, Jean-Olivier Plouchart, Ghavam G. Shahidi, Jeng-Bang Yau
  • Publication number: 20180053784
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 22, 2018
    Inventors: Jin CAI, Jean-Olivier PLOUCHART
  • Publication number: 20180053785
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?•cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 22, 2018
    Applicant: International Business Machines Corporation
    Inventors: Jin CAI, Jean-Olivier PLOUCHART
  • Patent number: 9899415
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jean-Olivier Plouchart
  • Publication number: 20180040597
    Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 8, 2018
    Inventors: Russell A. Budd, Mounir Meghelli, Jason Scott Orcutt, Jean-Olivier Plouchart
  • Patent number: 9880887
    Abstract: A method and device for allocating computer resources of a cluster for carrying out at least one job controlled by the cluster is disclosed. In one aspect, the method includes determining the placement of the job from physical features of the job and from physical features and availability of the computer resources of at least one processing area of the cluster. The method further includes receiving energy state features of the computer resources of at least the processing area; determining a recommended placement of the at least one job by correlating the physical features of the job, the physical features, availability and energy state of the computer resources on the basis of predetermined rules; and deducing, from the predetermined recommended placement, a recommended allocation list of the computer resources for carrying out the job in the cluster.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: January 30, 2018
    Assignee: BULL SAS
    Inventors: Jean-Olivier Gerphagnon, Françoise Mille-Rey, Corine Marchand
  • Publication number: 20180006855
    Abstract: A commutating circuit includes a single-ended mixer and a passive network. The single-ended mixer includes a differential local oscillator terminal. The passive network includes a plurality of inductors and a capacitor. The plurality of inductors can be coupled to the differential local oscillator terminal. The plurality of inductors can provide an impedance in accordance with a common mode or a differential mode. The commutating circuit can be implemented via a device, a system and/or a method.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: WOORAM LEE, JEAN-OLIVIER PLOUCHART, ALBERTO VALDES GARCIA
  • Publication number: 20170317848
    Abstract: A method of remote monitoring and remote control of a cluster including nodes connected to a communication network of a first type, a relay node of the nodes including first and second network interfaces in accordance with first and second types of communication network respectively, the first and second types being distinct, some steps of the monitoring and control method being implemented in a remote computer linked to the relay node by a communication network of the second type, the method including receiving a packet via the first network interface; encapsulating the received data packet in a data frame in accordance with a protocol of the communication network of the second type; sending the data frame to the remote computer via the second network interface, the receiving of the data packet, the encapsulating of the data packet and the sending of the data frame being implemented in the relay node.
    Type: Application
    Filed: November 3, 2015
    Publication date: November 2, 2017
    Applicant: BULL SAS
    Inventors: Jean-Vincent FICET, Sébastien DUGUE, Jean-Olivier GERPHAGNON
  • Publication number: 20170315936
    Abstract: For the management of a file system for accessing data in a storage system in which the data are stored physically in a unique manner, a first storage environment associated with a first access performance level is mounted, from a first mount point. Moreover, at least one second storage environment, different from the first storage environment, and associated with a second access performance level is mounted, from a second mount point and with total or partial overlay of data with respect to the first storage environment. The data physically stored in a unique manner in the storage system is accessed, either via the first mount point or via the second mount point, as a function of a data use case.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 2, 2017
    Inventors: Jean-Olivier GERPHAGNON, Grégoire PICHON, Ludovic SAUGE
  • Publication number: 20170308388
    Abstract: A screen copying method including the copying, in the form of an image file, of a portion of an image displayed on a screen where a user graphically selects the image portion, the copying of the selected image portion automatically resulting in: the copying of the pointer or pointers associated with the image portion along with the coordinates of the pointers in the image portion, the pointers respectively pointing to objects; and the maintaining of the respective links between the pointers and the coordinates so that, during a subsequent redisplay of the image portion on a screen, the graphical selection of a point corresponding to one of the coordinates by a user automatically activates the pointer corresponding to the coordinate of the selected point and brings up the object corresponding to the activated pointer.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 26, 2017
    Inventors: Jean-Olivier GERPHAGNON, Liana BOZGA, David ENGUEHARD