Patents by Inventor Jean Philippe Laine
Jean Philippe Laine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490243Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.Type: GrantFiled: August 22, 2012Date of Patent: November 8, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jean Philippe Laine, Patrice Besse
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Patent number: 9478531Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.Type: GrantFiled: August 3, 2012Date of Patent: October 25, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jean Philippe Laine, Patrice Besse
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Publication number: 20160300832Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.Type: ApplicationFiled: November 22, 2013Publication date: October 13, 2016Inventors: Patrice Besse, Jean-Philippe Laine, Eric Pierre Rolland
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Publication number: 20160285261Abstract: An electrostatic discharge (ESD) device is disclosed having two PNP transistors. During a high-voltage ESD event a parasitic NPN transistor couples to one of the two PNP transistors to provide ESD protection.Type: ApplicationFiled: August 26, 2015Publication date: September 29, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: JEAN PHILIPPE LAINE, PATRICE BESSE
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Publication number: 20160276335Abstract: An ESD protection device comprising an SCR -type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents.Type: ApplicationFiled: October 18, 2013Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20160276460Abstract: An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.Type: ApplicationFiled: August 19, 2015Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20160276332Abstract: An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.Type: ApplicationFiled: August 19, 2015Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Electrostatic discharge protection circuit arrangement, electronic circuit and ESD protection method
Patent number: 9438031Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.Type: GrantFiled: February 29, 2012Date of Patent: September 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jerome Casters, Jean-Philippe Laine, Alain Salles -
Publication number: 20160156180Abstract: An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimise the breakdown resistance of the circuit.Type: ApplicationFiled: May 4, 2015Publication date: June 2, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: PATRICE BESSE, PHILIPPE GIVELIN, JEAN PHILIPPE LAINE
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Publication number: 20150311193Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.Type: ApplicationFiled: August 22, 2012Publication date: October 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20150221633Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.Type: ApplicationFiled: August 3, 2012Publication date: August 6, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jean Philippe Laine, Patrice Besse
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Publication number: 20150221629Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.Type: ApplicationFiled: September 12, 2012Publication date: August 6, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Alexis Huot-Marchand, Jean-Philippe Laine, Alain Salles
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ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT ARRANGEMENT, ELECTRONIC CIRCUIT AND ESD PROTECTION METHOD
Publication number: 20150049406Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.Type: ApplicationFiled: February 29, 2012Publication date: February 19, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jerome Casters, Jean-Philippe Laine, Alain Salles -
Patent number: 8680621Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.Type: GrantFiled: May 18, 2010Date of Patent: March 25, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jean Philippe Laine
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Publication number: 20130056792Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.Type: ApplicationFiled: May 18, 2010Publication date: March 7, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jean Philippe Laine
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Patent number: 8334575Abstract: A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device.Type: GrantFiled: October 3, 2008Date of Patent: December 18, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jean Philippe Laine, Patrice Besse, Alexis Huot-Marchand
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Publication number: 20110180876Abstract: A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device.Type: ApplicationFiled: October 3, 2008Publication date: July 28, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jean Philippe Laine, Patrice Besse, Alexis Huot-Marchand