Patents by Inventor Jean-Pierre Bouzidi

Jean-Pierre Bouzidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7929469
    Abstract: The present invention relates to a method for attenuating near-end crosstalk between a remote received signal and a locally transmitted signal in a bidirectional signal transmission wherein said method comprises the step of producing an analog automatic feedback-driven correction loop in order to provide a no-correlation between said transmitted and received signals and to a hybrid circuit for enabling said method.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: April 19, 2011
    Assignee: Alcatel-Lucent
    Inventor: Jean-Pierre Bouzidi
  • Publication number: 20090270039
    Abstract: The present invention relates to a method for attenuating near-end crosstalk between a remote received signal and a locally transmitted signal in a bidirectional signal transmission wherein said method comprises the step of producing an analog automatic feedback-driven correction loop in order to provide a no-correlation between said transmitted and received signals and to a hybrid circuit for enabling said method.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 29, 2009
    Inventor: Jean-Pierre Bouzidi
  • Patent number: 7054439
    Abstract: According to the invention, means for reducing the interference caused by a voltage or a current in common mode, comprise adders (S3; S4) in each path for adding a first counter-reaction voltage (V1) to the voltage of the relevant path, a bridge (R1, R2) and an inverter (I3) for provision of said first counter-reaction voltage which is equal to half the sum of the voltages (VA, VB), respectively supplied to the inputs (A; B), with an opposing sign. According to the invention, the effect of a delay introduced by the inverter (I3) may be reduced, whereby said stage further comprises means (S5; S6) for adding in addition to the input voltage for each path, a second counter-reaction voltage (Va1; Vb1), and means (R1, R2, I1, S1; I2, S2) for provision of a second counter-reaction voltage (Va1; Vb1) which is a function of the input voltage (VA; VB) at the input corresponding to said path, with an opposing sign and with a delay identical to that generated by the inverter (I3).
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: May 30, 2006
    Assignee: Alcatel
    Inventor: Jean-Pierre Bouzidi
  • Publication number: 20050142953
    Abstract: A regulator for impedance balancing of a transmission wire pair The present invention relates to a regulator for impedance balancing of first (104) and second wires (106) of a transmission wire pair having respective first and second impedances, the regular comprising: means (108) for determining a first signal (116) being representative of an average of square value of a first current (i1) flowing through the first wire, means (118) for determining a second signal (126) being representative of the average of square value of a second current (i2) flowing through the second wire, means (128, 130) for determining first and second coefficients (k1, k2) on the basis of the first and second signals, first feedback means (132,134, 136) for regulating the first current on the basis of the first coefficient, second feedback means (138,140,142) for regulating the second current on the basis of the second coefficient.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 30, 2005
    Inventor: Jean-Pierre Bouzidi
  • Publication number: 20050063537
    Abstract: According to the invention, means for reducing the interference caused by a voltage or a current in common mode, comprise adders (S3; S4) in each path for adding a first counter-reaction voltage (V1) to the voltage of the relevant path, a bridge (R1, R2) and an inverter (I3) for provision of said first counter-reaction voltage which is equal to half the sum of the voltages (VA, VB), respectively supplied to the inputs (A; B), with an opposing sign. According to the invention, the effect of a delay introduced by the inverter (I3) may be reduced, whereby said stage further comprises means (S5; S6) for adding in addition to the input voltage for each path, a second counter-reaction voltage (Va1; Vb1), and means (R1, R2, I1, S1; I2, S2) for provision of a second counter-reaction voltage (Va1; Vb1) which is a function of the input voltage (VA; VB) at the input corresponding to said path, with an opposing sign and with a delay identical to that generated by the inverter (I3).
    Type: Application
    Filed: January 14, 2003
    Publication date: March 24, 2005
    Inventor: Jean-Pierre Bouzidi
  • Patent number: 6728373
    Abstract: The stage includes two channels each connecting an input to an output. Each channel includes a first device for adding to the input voltage of the channel concerned a feedback voltage from the other channel to the channel concerned. For remote power feeding a terminal, the stage further includes respective means in each channel for adding a DC voltage to the output voltage of that channel. The feedback voltage is a function only of the AC component of the output voltage of the first device of the channel concerned. Application to telephone exchanges.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: April 27, 2004
    Assignee: Alcatel
    Inventor: Jean-Pierre Bouzidi
  • Patent number: 5684844
    Abstract: The relates to locking the phase of output signal (Ys) relative to an input signal (Ye). A first frequency correction signal (Yr1) is obtained by integrating a signal representative of an error of said phase relative to a reference defined by the input signal. It then cooperates with a second frequency correction signal (Yr2) to correct the frequency of an oscillator (VCO) supplying the output signal. The second frequency correction signal is obtained with the help of an adjustment signal (Yg) by integrating an error of the first frequency correction signal (Yr1) relative to said adjustment signal. The adjustment signal may itself be obtained by integrating a frequency error. The invention is particularly applicable to telecommunications systems.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: November 4, 1997
    Assignee: Alcatel CIT
    Inventors: Jean-Pierre Bouzidi, Joseph Ropars
  • Patent number: 5150071
    Abstract: A differential output stage for electronic equipment, the output stage comprising a two-port network having two paths, each connecting an input terminal to an output terminal, and comprising means for generating a negative feedback voltage from each path for application to the other, and means for providing an output voltage in each path equal to an identical linear combination in each path, of the input voltage to the path and of the negative feedback voltage from the other path.
    Type: Grant
    Filed: March 21, 1991
    Date of Patent: September 22, 1992
    Assignee: Alcatel Cit
    Inventor: Jean-Pierre Bouzidi