Phase-locking method and a loop applying the method

- Alcatel CIT

The relates to locking the phase of output signal (Ys) relative to an input signal (Ye). A first frequency correction signal (Yr1) is obtained by integrating a signal representative of an error of said phase relative to a reference defined by the input signal. It then cooperates with a second frequency correction signal (Yr2) to correct the frequency of an oscillator (VCO) supplying the output signal. The second frequency correction signal is obtained with the help of an adjustment signal (Yg) by integrating an error of the first frequency correction signal (Yr1) relative to said adjustment signal. The adjustment signal may itself be obtained by integrating a frequency error. The invention is particularly applicable to telecommunications systems.

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Claims

1. A method of phase-locking an output signal (Ys) relative to an input signal (Ye), said method comprising the steps of obtaining a first frequency correction signal (Yr1) by integrating a signal representative of an error in the phase of said output signal relative to a phase of said input signal, and then correcting the frequency of an oscillator (VCO) supplying said output signal in accordance with said first frequency correction signal and a second frequency correction signal (Yr2),

said method being characterized in that said second frequency correction signal (Yr2) is obtained by integrating an error of the first frequency correction signal (Yr1) relative to an adjustment signal (Yg).

2. A phase-locked loop comprising:

an input (E) for receiving an alternating input signal (Ye) having an input frequency (fe) and defining a reference phase;
a phase comparator (CP) responsive firstly to said reference phase and secondly to the phase of an alternating output signal (Ys) having an output frequency (fs), said comparator supplying a phase error signal (Yc) representative of a phase error (.theta.s) presented by the output signal relative to the reference phase;
a phase error integrator (I1) receiving and integrating said phase error signal to provide a first frequency correction signal (Yr1);
frequency error compensation means providing a second frequency correction signal (Yr2); and
a loop oscillator (VCO) having a natural frequency (f0) and receiving the first and second frequency correction signals, said oscillator supplying said output signal (Ys) and inserting between its said natural frequency and said output frequency (fs) a difference that increases with said first and second frequency correction signals and that presents a direction suitable for reducing said phase error;
said loop being characterized by the fact that said frequency error compensation means comprise:
adjustment means for supplying an adjustment signal (Yg);
an adder (A) receiving both said first frequency correction signal and said adjustment signal, and subtracting said adjustment signal from the first correction signal to supply a compensation error signal; and
a compensation integrator (I2) receiving and integrating the compensation error signal to supply the second frequency correction signal.

3. A loop according to claim 2, characterized by the fact that said adjustment means comprise:

a frequency comparator (Cf) responsive firstly to said input frequency (fe) and secondly to said output frequency (fs) and supplying in response thereto a frequency error signal representative of a frequency error presented by said output frequency relative to said input frequency; and
a frequency error integrator (I3) receiving and integrating said frequency error signal to supply said adjustment signal (Yg) by making said adjustment signal vary in a direction that is suitable for reducing said frequency error.
Referenced Cited
U.S. Patent Documents
4297728 October 27, 1981 Lowe
4404530 September 13, 1983 Stryer
4686689 August 11, 1987 Rorden
4745371 May 17, 1988 Haine
5319680 June 7, 1994 Port et al.
5570398 October 29, 1996 Smith
Foreign Patent Documents
0155396A3 September 1985 EPX
Patent History
Patent number: 5684844
Type: Grant
Filed: May 30, 1996
Date of Patent: Nov 4, 1997
Assignee: Alcatel CIT (Paris)
Inventors: Jean-Pierre Bouzidi (Lannion), Joseph Ropars (Lannion)
Primary Examiner: Stephen Chin
Assistant Examiner: Joseph Roundtree
Law Firm: Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
Application Number: 8/655,143
Classifications