Patents by Inventor Jean Yee-Mei Yang
Jean Yee-Mei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9318333Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.Type: GrantFiled: March 16, 2007Date of Patent: April 19, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
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Publication number: 20130228851Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: April 8, 2013Publication date: September 5, 2013Applicant: SPANSION LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 8415734Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: GrantFiled: December 7, 2006Date of Patent: April 9, 2013Assignee: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 7977218Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.Type: GrantFiled: December 26, 2006Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
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Patent number: 7553727Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.Type: GrantFiled: March 16, 2007Date of Patent: June 30, 2009Assignee: Spansion LLCInventors: Ming-Sang Kwan, Bradley Marc Davis, Jean Yee-Mei Yang, Zhizheng Liu, Yi He
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Publication number: 20080157199Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.Type: ApplicationFiled: March 16, 2007Publication date: July 3, 2008Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
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Publication number: 20080150006Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.Type: ApplicationFiled: March 16, 2007Publication date: June 26, 2008Inventors: Ming-Sang Kwan, Bradley Marc Davis, Jean Yee-Mei Yang, Zhizheng Liu, Yi He
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Publication number: 20080153269Abstract: The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
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Publication number: 20080135913Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Applicant: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 7163860Abstract: The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.Type: GrantFiled: May 6, 2003Date of Patent: January 16, 2007Assignee: Spansion LLCInventors: Tazrien Kamal, Yun Wu, Mark Ramsbey, Jean Yee-Mei Yang, Arvind Halliyal, Rinji Sugino, Hidehiko Shiraiwa, Fred T K Cheung
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Patent number: 7098546Abstract: The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.Type: GrantFiled: June 16, 2004Date of Patent: August 29, 2006Assignee: Fasl LLCInventors: Emmanuil H. Lingunis, Jean Yee-Mei Yang, Hidehiko Shiraiwa
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Patent number: 7078749Abstract: According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.Type: GrantFiled: July 11, 2003Date of Patent: July 18, 2006Assignee: Spansion LLCInventors: Jean Yee-Mei Yang, Yider Wu
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Patent number: 7052961Abstract: According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.Type: GrantFiled: December 3, 2004Date of Patent: May 30, 2006Assignee: Spansion LLCInventors: Hidehiko Shiraiwa, Jean Yee-Mei Yang, Jaeyong Park, Cyrus E. Tabery
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Patent number: 7023046Abstract: Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 ? to 600 ?, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.Type: GrantFiled: July 11, 2003Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Angela Hui, Ning Cheng, Jeyong Park, Jean Yee-Mei Yang, Robert A. Huertas, Tazrien Kamal, Pei-Yuan Gao, Tyagamohan Gottipati
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Patent number: 6989320Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.Type: GrantFiled: May 11, 2004Date of Patent: January 24, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Weidong Qian, Mark Ramsbey, Jean Yee-Mei Yang, Sameer Haddad
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Patent number: 6987048Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.Type: GrantFiled: August 6, 2003Date of Patent: January 17, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Ning Cheng, Hiroyuki Kinoshita, Jeff P. Erhardt, Mark T. Ramsbey, Cyrus Tabery, Jean Yee-Mei Yang
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Publication number: 20050255651Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.Type: ApplicationFiled: May 11, 2004Publication date: November 17, 2005Inventors: Weidong Qian, Mark Ramsbey, Jean-Yee-Mei Yang, Sameer Haddad
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Patent number: 6897533Abstract: A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.Type: GrantFiled: September 18, 2002Date of Patent: May 24, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Jean Yee-Mei Yang, Yider Wu
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Patent number: 6869844Abstract: A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.Type: GrantFiled: November 5, 2003Date of Patent: March 22, 2005Assignee: Advanced Micro Device, Inc.Inventors: Zhizheng Liu, Yider Wu, Jean Yee-Mei Yang
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Patent number: 6855608Abstract: A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls.Type: GrantFiled: June 17, 2003Date of Patent: February 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Mark Ramsbey, Mark W. Randolph, Jean Yee-Mei Yang, Hiroyuki Kinoshita, Cyrus Tabery, Jeff P. Erhardt, Tazrien Kamal, Jaeyong Park, Emmanuil H. Lingunis