Abstract: Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.

Abstract: A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.

Abstract: According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.

Abstract: One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A method of fabricating a charge trapping dielectric memory cell array comprises exposing a first photoresist to a first illumination pattern from a first mask to pattern bit line regions in a core region of the wafer and to pattern alignment mark regions. The alignment mark regions may be in a scribe lane region of the wafer. An impurity is implanted into the wafer within the bit line regions and the alignment mark regions and an oxide is grown on the surface of the wafer in the scribe lane region to produce oxide protrusions within the alignment mark regions. A second photoresist is exposed to a second illumination pattern from a second mask to pattern word line regions within the core region of the wafer and utilizing surface height variations of the oxide protrusions to detect alignment between the second mask and the first mask.

Abstract: A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third