Patents by Inventor Jeff A. Bullington
Jeff A. Bullington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040114642Abstract: Wafer scale processing techniques produce chip-laser-diodes with an active region (62) and a diffraction grating (76) that redirects output light out the top and/or bottom surfaces. The diffraction grating (76) redirects a novel feedback from the optical output (e.g., fiber (74)) to produce lasing that self-aligns itself to the fiber input, reducing assembly costs. Preferably, a diffraction grating (76) and integrated lens-grating are used herein to couple light from the chip to an output fiber (74), and the lens-grating is spaced from the diffraction grating (76). Combination grating and additional gratings and/or integrated lenses on the top or bottom of the diode can also be made utilizing wafer scale processes.Type: ApplicationFiled: September 19, 2003Publication date: June 17, 2004Inventors: Jeff A. Bullington, Richard A. Stoltz, Laurent Vaissie, Eric G. Johnson
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Publication number: 20020192850Abstract: These laser diode chips generate light parallel to the top surface and utilize gratings that diffract light out top and/or bottom surfaces. Thus they have both a long light generation region and a large output area, and can provide significantly higher power than prior art semiconductor-chip diodes. The chips utilize graded index (GRIN) layers to provide light containment in the core. Previously, such GRIN layers have not been doped. We have found that doping of a portion of the graded layers generally lowers resistance and increases efficiency of the semiconductor structure while retaining the light containment effectiveness of full-wavelength-height waveguide. Lowering resistance generally also lowers heat generation and thus increases reliability.Type: ApplicationFiled: May 16, 2002Publication date: December 19, 2002Inventors: Richard A. Stoltz, Jeff A. Bullington
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Publication number: 20020191666Abstract: Our wafer scale processing techniques produce chip-laser-diodes with a diffraction grating that redirects output light out the top and/or bottom surfaces. Noise reflections are carefully controlled, allowing significant reduction of the signal fed to the active region. This can be an improved method of diode fabrication where the top metal contact has a portion of the contact adjacent the top electrode that is of tungsten metal. The tungsten metal is preferably CVD tungsten. Photoresist has preferably been deposited prior to the deposition of the CVD tungsten and the pattern for the metal contact is opened in the photoresist, and then the CVD tungsten is deposited, and then the photoresist is removed, also removing any tungsten deposited on the photoresist. Preferably the CVD tungsten is deposited by using hydrogen reduction of tungsten hexafluoride.Type: ApplicationFiled: March 22, 2002Publication date: December 19, 2002Inventors: Richard A. Stoltz, Jeff A. Bullington
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Publication number: 20020192849Abstract: This is a diode-laser chip that utilizes a very low feedback. It utilizes a manufacturable grating that couples output light “vertically” out of a horizontal, active-region-containing core, and can minimize reflections that would cause loss and noise. This coupling grating can also feed back synchronizing light into the active region, while reducing the stray reflections that would cause the diode to produce light at unwanted frequencies. The angle of an external (e.g., partially reflecting) mirror provides light wavelength tuning and the mirror also provides the far end of the laser cavity. A positioner may be used to provide a relative angle between the fiber-axis and the horizontal diffracting grating, and standard semiconductor chips are manufactured and different nominal wavelength of light devices are produced by selecting different relative angle positioners.Type: ApplicationFiled: March 22, 2002Publication date: December 19, 2002Inventors: Jeff A. Bullington, Richard A. Stoltz
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Publication number: 20020182763Abstract: Our wafer scale processing techniques produce chip-laser-diodes with a diffraction grating that redirects output light out the top and/or bottom surfaces. Noise reflections are carefully controlled, allowing significant reduction of the signal fed to the active region. This can provide an improved method of horizontally generating light within a chip-laser-diode and transmitting a substantial portion of the generated light vertically out of the diode, using a disordered waveguide-region. Generally, the waveguide region is disordered by rapid-thermal-annealing. Preferably, the disordering of the waveguide region by rapid-thermal-annealing is done while masking portions of the diode other than the waveguide region with photoresist or with a mechanical mask, and preferably is done with light passed through an optical pass filter designed to pass the output wavelength of the diode.Type: ApplicationFiled: March 22, 2002Publication date: December 5, 2002Inventors: Richard A. Stoltz, Jeff A. Bullington
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Publication number: 20020176463Abstract: This narrow-band coherent light, (light that is virtually all in-phase and at, or essentially at, the same wavelength) grating-coupled, diode-chip-laser improvement enables, for the first time, combining the functional advantages of non-semiconductor-chip (e.g., fluid) lasers with the efficiency, economy, and convenience of semiconductor-chip-manufacturing (wafer processing), while providing significantly higher power than prior art semiconductor-chip diodes. It utilizes a manufacturable grating that couples output light “vertically” out of a horizontal, active-region-containing core, and generally minimizes reflections that would cause loss and noise. All reflections from the grating back into the active region are essentially eliminated (to less than 0.1% and preferably less than 0.01% of the light diffracted out of said structure).Type: ApplicationFiled: March 22, 2002Publication date: November 28, 2002Inventors: Jeff A. Bullington, Richard A. Stoltz, Oleg V. Smolski
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Publication number: 20020176464Abstract: Our wafer scale processing techniques produce chip-laser-diodes with a diffraction grating that redirects output light out the top and/or bottom surfaces. Noise reflections are carefully controlled, allowing significant reduction of the signal fed to the active region. In GaAs substrate embodiments, prior art gratings have generally been in AlGaAs. By using a InGaP layer epitaxially grown over (preferably directly on the top of) the core, our lasers can have an etch-stop-layer for accurate vertical location of the grating, and provides an aluminum-free grating (avoiding problems of aluminum oxidation), and also enables fabrication of saw-tooth gratings using anisotropic etching of InGaP.Type: ApplicationFiled: March 22, 2002Publication date: November 28, 2002Inventors: Oleg V. Smolski, Jeff A. Bullington
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Publication number: 20020092166Abstract: A planar heat sink, using heat pipe principals, is constructed by encapsulating a metalized heat fugitive plastic mandrel in a copper electroform bath and removing the plastic mandrel. The heat pipe chamber of the heat sink is constructed with a plurality of cruciform shaped vanes, wicking structures, for improved wetting and to prevent the formation of droplets. The plastic mandrel is injection molded having opposing negative front and back panels containing negative vanes. The core and cavity for the injection mold tool are formed by electroforming a machined aluminum plate which is etched by laser with the vane pattern.Type: ApplicationFiled: January 12, 2001Publication date: July 18, 2002Inventors: Paul F. Jacobs, Jeff Bullington
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Patent number: 5949071Abstract: A monolithic infrared detector structure which allows integration of pyroelectric thin films atop low thermal conductivity aerogel thin films. The structure comprises, from bottom to top, a substrate, an aerogel insulating layer, a lower electrode, a pyroelectric layer, and an upper electrode layer capped by a blacking layer. The aerogel can offer thermal conductivity less than that of air, while providing a much stronger monolithic alternative to cantilevered or suspended air-gap structures for pyroelectric thin film pixel arrays. Pb(Zr.sub.0.4 Ti.sub.0.6)O.sub.3 thin films deposited on these structures displayed viable pyroelectric properties, while processed at 550.degree. C.Type: GrantFiled: August 14, 1997Date of Patent: September 7, 1999Assignee: Sandia CorporationInventors: Judith A. Ruffner, Jeff A. Bullington, Paul G. Clem, William L. Warren, C. Jeffrey Brinker, Bruce A. Tuttle, Robert W. Schwartz
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Patent number: 5926412Abstract: Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.Type: GrantFiled: April 2, 1992Date of Patent: July 20, 1999Assignee: Raytheon CompanyInventors: Joseph T. Evans, Jr., Jeff A. Bullington, Stephen E. Bernacki, Bruce G. Armstrong
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Patent number: 5453347Abstract: A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO.sub.2 or Si.sub.3 N.sub.4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond the bottom electrode to the substrate surface.Type: GrantFiled: June 7, 1994Date of Patent: September 26, 1995Assignee: Radiant TechnologiesInventors: Jeff A. Bullington, Carl E. Montross, Jr., Joseph T. Evans, Jr.
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Patent number: 5440173Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800.degree. C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.Type: GrantFiled: September 17, 1993Date of Patent: August 8, 1995Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington
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Patent number: 5420428Abstract: The sensing array detects an image by measuring the changes in the dielectric constant of individual capacitors in a rectangular array of capacitors. The present invention avoids the use of isolation transistors to eliminate the effects of other capacitors in the array when measuring the capacitance of a given capacitor in the array. During the measurement of any given capacitor in the array, the present invention maintains a zero potential difference across the capacitors that are not being measured, thereby eliminating any interference that might be caused by these capacitors.Type: GrantFiled: May 5, 1993Date of Patent: May 30, 1995Assignee: Radiant Technologies, Inc.Inventors: Jeff A. Bullington, Joseph T. Evans, Jr., Carl E. Montross, Jr.
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Patent number: 5242534Abstract: A method for generating platinum features on the surface of a substrate is disclosed. The method provides an inexpensive means for constructing small platinum features. The method utilizes a photoresist mask to define the platinum features. The problems associated with residue from the deposition of the photoresist mask are overcome by utilizing an etching step which removes any such residue. The etching step also allows the platinum features to be recessed into the substrate surface.Type: GrantFiled: September 18, 1992Date of Patent: September 7, 1993Assignee: Radiant TechnologiesInventors: Jeff A. Bullington, Carl E. Montross, Jr.
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Patent number: 5239399Abstract: Devices for converting digital data into a light pulse train and decoding such a pulse train are disclosed. The light pulse generating device generates a train of light pulses having a pattern determined by a numerical value represented by a plurality of binary bits. The light pulse train generating device stores the bits in a register. Each cell of the register is connected to a light switching device that will interrupt a first light beam in response to a light signal if the value stored in the cell is a logical one. If the value is a logical 0, the interruption will not occur. The decoding device utilizes a plurality of light activated switches to route individual pulses in the light pulse train to different photodetectors. The light activated switching devices avoid the delays inherent in electrically activated switching devices.Type: GrantFiled: August 22, 1991Date of Patent: August 24, 1993Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington
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Patent number: 5212620Abstract: An improved method for constructing integrated circuit structures in which a buffer SiO.sub.2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO.sub.2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO.sub.2 which is commonly observed when the SiO.sub.2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO.sub.2 layer from the ferroelectric material and/or the platinum regions.Type: GrantFiled: March 3, 1992Date of Patent: May 18, 1993Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington, Carl E. Montross, Jr.
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Patent number: 5179533Abstract: An improved read/write optical disk is disclosed which is capable of being rewritten more than 10.sup.6 times. The disk utilizes a storage medium in which data is stored by causing a localized region of the storage medium to assume one of two states. The two states can be converted from one to another by the application of electric fields to the localized region of the storage medium. The localized region in question is selected by illuminating an area on an addressing layer directly above the region in question with light. The preferred embodiment utilizes a lead lanthanum zirconate titanate material for the storage medium.Type: GrantFiled: July 31, 1989Date of Patent: January 12, 1993Assignee: Radiant TechnologiesInventors: Jeff A. Bullington, Sylvia D. Mancha, Christopher DeHainaut
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Patent number: 5164808Abstract: An improved ferroelectric structure and the method for making the same is disclosed. The improved structure reduces the fatigue problems encountered in ferroelectric capacitors while providing avoiding problems in depositing the ferroelectric material which have prevented other solutions to the fatigue problem from being effective. The improved ferroelectric structure also provides improved adhesion to the underlying substrate. The ferroelectric structure has a bottom electrode comprising a layer of PtO.sub.2 which is generated by depositing a layer of Platinum on a suitable substrate and then exposing the Platinum layer to an Oxygen plasma. The ferroelectric material is then deposited on the PtO.sub.2 layer.Type: GrantFiled: August 9, 1991Date of Patent: November 17, 1992Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington, Carl E. Montross, Jr.
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Patent number: 5119329Abstract: An improved memory device based on a non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferro-electric layer. The semiconductor forms one plate of a parallel plate capacitor having a dielectric comprising the ferro-electric layer. The state of the memory device is determined by measuring the resistivity of the semiconductor layer between two contacts on the semiconductor layer. The state of polarization of the ferro-electric layer is altered by applying a voltage between one of these contacts and the other plate of the capacitor.Type: GrantFiled: May 13, 1991Date of Patent: June 2, 1992Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington
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Patent number: 5109156Abstract: A light activated AND gate is disclosed which generates a light signal at a first output port in response to the simultaneous presence of light signals at an input port and a control port. With a light signal present at the control port, a light beam at the input port is reflected from an interface between two regions having different indices of refraction, and the reflected light beam then exits through a first output port. In the absence of a light signal at the control port, the two regions of the switching device have the same index of refraction, and the light beam at the input port passes through both regions and exits through a second output port.Type: GrantFiled: October 25, 1990Date of Patent: April 28, 1992Assignee: Radiant Technologies, Inc.Inventors: Joseph T. Evans, Jeff A. Bullington