Abstract: In an example, a chip-scale atomic clock physics package is provided. This chip-scale atomic clock physics package includes a body defining a cavity, and a first scaffold mounted in the cavity. A laser is mounted on the first surface of the first scaffold. A second scaffold is also mounted in the cavity. The second scaffold is disposed such that the first surface of the second scaffold is facing the first scaffold. A first photodetector is mounted on the first surface of the second scaffold. A vapor cell is mounted on the first surface of the second scaffold. A waveplate is also included, wherein the laser, waveplate, first photodetector, and vapor cell are disposed such that a beam from the laser can propagate through the waveplate and the vapor cell and be detected by the first photodetector. A lid is also included for covering the cavity.

Abstract: A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

Abstract: A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

Abstract: A method to construct a chip-scale atomic clock is provided. The method comprises providing a scaffolding for components in a chip-scale atomic clock. The components include a laser and at least one other component. The method also includes operationally positioning the components on the scaffolding so that an emitting surface of the laser is non-parallel to partially reflective surfaces of the at least one other component.

Abstract: Designs and processes for thermally stabilizing a vertical cavity surface emitting laser (vcsel) in a chip-scale atomic clock are provided. In one embodiment, a Chip-Scale Atomic Clock includes: a vertical cavity surface emitting laser (vcsel); a heater block coupled to a base of the vcsel; a photo detector; a vapor cell, wherein the vapor cell includes a chamber that defines at least part of an optical path for laser light between the vcsel and the photo detector; and an iso-thermal cage surrounding the vcsel on all sides, the iso-thermal cage coupled to the heater block via a thermally conductive path.

Abstract: A process for packaging micro-electro-mechanical systems (MEMS) devices comprises providing a lower cover wafer and an upper cover wafer, providing a semiconductor wafer including a plurality of MEMS devices on a substrate layer, bonding the semiconductor wafer to a first surface of the lower cover wafer, and bonding a second surface of the upper cover wafer to the semiconductor wafer. The first surface of the lower cover wafer and the second surface of the upper cover wafer define a plurality of hermetically sealed cavity sections when bonded to the semiconductor wafer such that each of the MEMS devices is located inside one of the sealed cavity sections. A plurality of holes are formed that extend from the first surface of the upper cover wafer to the second surface of the upper cover wafer after the upper cover wafer is bonded to the semiconductor wafer. A metal lead layer is then deposited in each of the holes to provide an electrical connection with the MEMS devices.

Abstract: Devices, methods, and systems for wafer bonding are described herein. One or more embodiments include forming a bond between a first wafer and a second wafer using a first material adjacent the first wafer and a second material adjacent the second wafer. The first material includes a layer of gold (Au) and a layer of indium (In), and the second material includes a layer of Au. Forming the bond between the first wafer and the second wafer includes combining the layer of Au in the first material, the layer of In in the first material, and a portion of the layer of Au in the second material, wherein an additional portion of the layer of Au in the second material is not combined with the layer of Au in the first material and the layer of In in the first material.

Abstract: A chip-scale atomic clock comprises a physics package and a laser die located in a first thermal zone of the physics package. A quarter wave plate is mounted in the physics package and is in optical communication with the laser die. A vapor cell is mounted in the physics package and is in optical communication with the quarter wave plate. The vapor cell is located in a second thermal zone that is independent from the first thermal zone. An optical detector is mounted in the physics package and is in optical communication with the vapor cell. The first thermal zone provides a first operation temperature at a first stability point associated with the laser die, and the second thermal zone provides a second operation temperature at a second stability point associated with the vapor cell.

Abstract: A method of fabricating a multi-axis sensor is provided. The method includes forming patterns of sacrificial material overlaying a substrate and overlaying a flexible material on the sacrificial material and an anchor-surface of the substrate. The flexible material includes sensor-regions, an anchor-region, and at least one hinge-region. The method further includes forming sensor elements from orientable sensor material overlaying respective sensor-regions of the flexible material; forming at least one respective anchor-hinge in the flexible material along the boundary between the anchor-region and an adjacent sensor region; forming the sensor-regions, the anchor-region, and the at least one hinge-region in the flexible material; training the sensor elements to form respective oriented-sensor elements that are oriented in the same direction; etching the sacrificial material; and etching the substrate at an angle from the anchor-surface.

Abstract: Designs and processes for thermally stabilizing a vertical cavity surface emitting laser (vcsel) in a chip-scale atomic clock are provided. In one embodiment, a Chip-Scale Atomic Clock includes: a vertical cavity surface emitting laser (vcsel); a heater block coupled to a base of the vcsel; a photo detector; a vapor cell, wherein the vapor cell includes a chamber that defines at least part of an optical path for laser light between the vcsel and the photo detector; and an iso-thermal cage surrounding the vcsel on all sides, the iso-thermal cage coupled to the heater block via a thermally conductive path.

Abstract: A chip-scale atomic clock comprises a physics package and a laser die located in a first thermal zone of the physics package. A quarter wave plate is mounted in the physics package and is in optical communication with the laser die. A vapor cell is mounted in the physics package and is in optical communication with the quarter wave plate. The vapor cell is located in a second thermal zone that is independent from the first thermal zone. An optical detector is mounted in the physics package and is in optical communication with the vapor cell. The first thermal zone provides a first operation temperature at a first stability point associated with the laser die, and the second thermal zone provides a second operation temperature at a second stability point associated with the vapor cell.

Abstract: A method to construct a chip-scale atomic clock is provided. The method comprises providing a scaffolding for components in a chip-scale atomic clock. The components include a laser and at least one other component. The method also includes operationally positioning the components on the scaffolding so that an emitting surface of the laser is non-parallel to partially reflective surfaces of the at least one other component.

Abstract: A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

Abstract: Apparatus and methods for alkali vapor cells are provided. In one embodiment, a vapor cell for a Chip-Scale Atomic Clocks (CSAC) comprises a silicon wafer having defined within a first chamber, a second chamber, and a pathway connecting the first chamber to the second chamber; a first glass wafer anodically-bonded to a first surface of the silicon wafer; a second glass wafer anodically-bonded to an opposing second surface of the silicon wafer, wherein the first chamber defines an optical path through the vapor cell; and an alkali metal material deposited into the second chamber. The pathway connecting the first chamber to the second chamber is configured with a geometry that is at least partially inhibitive to alkali metal vapor flow.

Abstract: An improved MEMS device and method of making. Channels are formed in a first substrate around a plurality of MEMS device areas previously formed on the first substrate. Then, a plurality of seal rings are applied around the plurality of MEMS device areas and over at least a portion of the formed channels. A second substrate is attached to the first substrate, then the seal ring surrounded MEMS device areas are separated from each other. The channels include first and second cross-sectional areas. The first cross-sectional area is sized to keep saw debris particles from entering the MEMS device area.

Abstract: A hermetically sealed MEMS device package comprises a MEMS device platform, a hermetic interface chip, and an outer seal ring. The MEMS device platform includes a MEMS device surrounded by a continuous outer boundary wall with a top surface. The hermetic interface chip includes a glass substrate and at least one silicon mesa. The glass substrate includes at least one hole and has a lower surface with an inner portion surrounded by an outer portion. The at least one silicon mesa is bonded to the inner portion of the lower surface of the glass substrate, such that the at least one silicon mesa is aligned with the at least one hole in the glass substrate. The outer seal ring bonds the outer portion of the lower surface of the glass substrate to the top surface of the continuous outer boundary wall of the MEMS device platform.

Abstract: Systems and methods for MEMS device fabrication. A layer of photoresist is formed on a substrate. A first region of the substrate is exposed to a radiation source through a photomask. The first region of exposed photoresist is developed with a developer solution in order to etch the exposed regions to a first depth. A second region is exposed to radiation through a second photomask. The second photomask defines areas in which a bump feature is intended on the substrate. The second region is developed with the developer solution, preparing the first and second exposed regions for a layer of metal. A layer of metal is deposited on the substrate, such that the metal attaches to both the substrate and any remaining photoresist on the substrate. The remaining photoresist and its attached metal is dissolved away leaving an interconnect pattern and at least one bump feature.

Abstract: Systems and methods for reducing stiction between elements of a microelectromechanical systems (MEMS) device during anodic bonding. The MEMS device includes a substrate cover with an optional conductor on its interior surface and the cover is anchored to a first portion of a sensing element. The MEMS device further includes a second portion of the sensing element separated from the substrate cover with a space and an antistiction element disposed between the second portion and cover. The antistiction element can be formed of a material type with high electrostatic resistance, to prevent stiction between MEMS device elements during anodic bonding.

Abstract: An improved MEMS device and method of making. Channels are formed in a first substrate around a plurality of MEMS device areas previously formed on the first substrate. Then, a plurality of seal rings are applied around the plurality of MEMS device areas and over at least a portion of the formed channels. A second substrate is attached to the first substrate, then the seal ring surrounded MEMS device areas are separated from each other. The channels include first and second cross-sectional areas. The first cross-sectional area is sized to keep saw debris particles from entering the MEMS device area.

Abstract: A MEMS device includes a P-N device formed on a silicon pin, which is connected to a silicon sub-assembly, and where the P-N device is formed on a silicon substrate that is used to make the silicon pin before it is embedded into a first glass wafer. In one embodiment, forming the P-N device includes selectively diffusing an impurity into the silicon pin and configuring the P-N device to operate as a temperature sensor.