Patents by Inventor Jeff Babcock

Jeff Babcock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8247862
    Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 21, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jeff A Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7808034
    Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: October 5, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jeff Babcock, Natasha Layrovskava, Yuri Mirgorodski, Saurahh Desai
  • Publication number: 20100157682
    Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Applicant: National Semiconductor Corporation
    Inventors: Jeff A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7719048
    Abstract: A heating element is utilized to improve the bias conditions of an E2PROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate and read transistor are set to ground. The heating element then has a voltage potential applied across its terminals, causing current to flow in this resistor. As the current density increases, the resistor begins to generate heat. This heat is thermally coupled into the cell's floating gate, causing its temperature to rise.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: May 18, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jeff A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7663173
    Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: February 16, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Saurabh Desai, Natasha Lavrovskaya, Yuri Mirgorodski, Jeff Babcock
  • Patent number: 7572708
    Abstract: A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewall also improves dopant loss in the oxide in the case in which an in-situ doped poly emitter is used. By using a doped sidewall glass, the sensitivity of dopant absorption that can potentially occur in un-doped spacers is removed. The proposed technique also provides a simple method for achieving narrow emitter window openings while simultaneously improving doping uniformity compared to implanted poly techniques. The technique also allows a self-aligned base to be performed, thereby allowing tighter spacing between the extrinsic base and the intrinsic base.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 11, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Jeff A. Babcock, Steve Adler, Todd Thiebeault, Jamal Ramdani
  • Patent number: 7307314
    Abstract: A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: December 11, 2007
    Assignee: Cree Microwave LLC
    Inventors: Jeff Babcock, Johan Agus Darmawan, John Mason, Ly Diep
  • Patent number: 7061057
    Abstract: Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: June 13, 2006
    Assignee: Cree Microwave, LLC
    Inventors: Jeff Babcock, Johan Agus Darmawan, John Mason
  • Publication number: 20050280087
    Abstract: An LDMOS transistor includes a source capacitor structure and a gate-drain shield which can be interconnected whereby the source capacitor can be grounded to provide an RF ground for the shield and whereby the RF shield can have a positive DC voltage bias to enhance laterally diffused drain conductance without increasing doping therein.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 22, 2005
    Applicant: CREE MICROWAVE, INC.
    Inventors: Jeff Babcock, Johan Darmawan, John Mason
  • Publication number: 20050280085
    Abstract: An LDMOS transistor includes a trench source capacitor structure and a gate-drain shield which can be interconnected whereby the source capacitor can be grounded to provide an RF ground for the shield and whereby the RF shield can have a positive DC voltage bias to enhance laterally diffused drain conductance without increasing doping therein. The trench capacitor structure can include one or more adjacent trenches to increase capacitor plate area.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 22, 2005
    Applicant: CREE MICROWAVE, INC.
    Inventors: Jeff Babcock, Johan Darmawan, John Mason
  • Publication number: 20050280080
    Abstract: A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 22, 2005
    Applicant: CREE MICROWAVE, INC.
    Inventors: Jeff Babcock, Johan Darmawan, John Mason, Ly Diep
  • Publication number: 20050280101
    Abstract: Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 22, 2005
    Applicant: CREE MICROWAVE, INC.
    Inventors: Jeff Babcock, Johan Darmawan, John Mason
  • Patent number: 6759592
    Abstract: Kaolin is added to the insulation (30) in a metal sheathed, mineral-insulated cables of the type used as a power cable, heating cable, or thermocouples where high temperature and an aggressive medium may exist, and which are typically produced by drawing down the cable. The preferred insulation for the invention is MgO. The addition of kaolin decreases moisture seepage into the insulation and consequent drop in insulation resistivity. It also reduces the loss of electrical resistance as temperature increases.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: July 6, 2004
    Assignee: Tyco Thermal Control UK Limited
    Inventors: Kevin Guangjun Cai, Mickael Blamire, Robert Stokes, Douglas Wilton, James Snape, Glyn Jones, Jeff Babcock, Ann Machan
  • Patent number: RE42403
    Abstract: Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: May 31, 2011
    Assignee: Rovec Acquisitions Ltd., LLC
    Inventors: Jeff Babcock, Johan Agus Darmawan, John Mason