Patents by Inventor Jeff J Xu
Jeff J Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097034Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 11855210Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: GrantFiled: February 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Publication number: 20220173245Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 11251303Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: GrantFiled: August 5, 2020Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 11171134Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: December 19, 2019Date of Patent: November 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10998442Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: GrantFiled: December 12, 2019Date of Patent: May 4, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Publication number: 20200365736Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: August 5, 2020Publication date: November 19, 2020Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 10818661Abstract: Methods for fabricating FinFETs with enhanced performance are disclosed herein. An exemplary method includes forming a first fin and a second fin having a trench defined therebetween. The first fin and the second fin each include a first semiconductor layer disposed over a second semiconductor layer. An isolation feature is formed in the trench between the first fin and the second fin. A gate structure is formed over the isolation feature, a first region of the first fin, and a first region of the second fin. The gate structure is disposed between second regions of the first fin and between second regions of the second fin. After recessing the first fin and the second fin, a third semiconductor layer is formed over the first fin and the second fin. In some embodiments, the third semiconductor layer extends over the isolation feature and merges the first fin and the second fin.Type: GrantFiled: November 1, 2019Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hao Chang, Jeff J. Xu
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Patent number: 10693003Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.Type: GrantFiled: May 19, 2017Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
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Publication number: 20200126985Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Publication number: 20200119196Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Publication number: 20200066721Abstract: Methods for fabricating FinFETs with enhanced performance are disclosed herein. An exemplary method includes forming a first fin and a second fin having a trench defined therebetween. The first fin and the second fin each include a first semiconductor layer disposed over a second semiconductor layer. An isolation feature is formed in the trench between the first fin and the second fin. A gate structure is formed over the isolation feature, a first region of the first fin, and a first region of the second fin. The gate structure is disposed between second regions of the first fin and between second regions of the second fin. After recessing the first fin and the second fin, a third semiconductor layer is formed over the first fin and the second fin. In some embodiments, the third semiconductor layer extends over the isolation feature and merges the first fin and the second fin.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Inventors: Chih-Hao Chang, Jeff J. Xu
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Patent number: 10522544Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: May 1, 2019Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10510887Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: GrantFiled: February 6, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 10468408Abstract: A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.Type: GrantFiled: February 19, 2018Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hao Chang, Jeff J. Xu
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Publication number: 20190259753Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10312236Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: November 27, 2017Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10090300Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.Type: GrantFiled: October 16, 2015Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeff J. Xu, Chih-Hao Chang
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Publication number: 20180175032Abstract: A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.Type: ApplicationFiled: February 19, 2018Publication date: June 21, 2018Inventors: Chih-Hao Chang, Jeff J. Xu
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Patent number: 9922827Abstract: A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor.Type: GrantFiled: May 15, 2015Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann