Patents by Inventor Jeff J Xu

Jeff J Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259753
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 10312236
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 10090300
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeff J. Xu, Chih-Hao Chang
  • Publication number: 20180175032
    Abstract: A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 21, 2018
    Inventors: Chih-Hao Chang, Jeff J. Xu
  • Patent number: 9922827
    Abstract: A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann
  • Publication number: 20180076198
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 15, 2018
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 9911735
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Chang, Jeff J. Xu
  • Patent number: 9831243
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Publication number: 20170263749
    Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 14, 2017
    Inventors: Chih-Hao Chang, Jeff J. XU, Chien-Hsun WANG, Chih Chieh YEH, Chih-Hsiang CHANG
  • Publication number: 20170148917
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: TSUNG-LIN LEE, CHIH-HAO CHANG, CHIH-HSIN KO, FENG YUAN, JEFF J. XU
  • Patent number: 9660082
    Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Patent number: 9647118
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manaufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 9564529
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 9425286
    Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hsiang Lin, Jeff J. Xu, Pang-Yen Tsai
  • Patent number: 9356109
    Abstract: A transistor includes a gate dielectric structure over a substrate and a work function metallic layer over the gate dielectric structure. The work function metallic layer is configured to adjust a work function value of a gate electrode of the transistor. The transistor also includes a silicide structure over the work function metallic layer. The silicide structure is configured to be independent of the work function value of the gate electrode of the transistor.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: May 31, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jeff J. Xu
  • Publication number: 20160104706
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 14, 2016
    Inventors: Jeff J. Xu, Chih-Hao Chang
  • Publication number: 20160079425
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventor: Jeff J. Xu
  • Publication number: 20160064381
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Chih-Hao Chang, Jeff J. Xu
  • Patent number: 9245970
    Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Publication number: 20150380554
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Tsung-Lin LEE, Chih-Hao CHANG, Chih-Hsin KO, Feng YUAN, Jeff J. XU