Patents by Inventor Jeff L. Warner

Jeff L. Warner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with power saving feature
    Patent number: 9806019
    Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Anis M. Jarrar, David R. Tipple, Jeff L. Warner
  • INTEGRATED CIRCUIT WITH POWER SAVING FEATURE
    Publication number: 20170084535
    Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: ANIS M. JARRAR, DAVID R. TIPPLE, JEFF L. WARNER
  • Active Tiling Placement for Improved Latch-up Immunity
    Publication number: 20140264728
    Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming, a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner
  • Active tiling placement for improved latch-up immunity
    Patent number: 8765607
    Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner
  • Active Tiling Placement for Improved Latch-Up Immunity
    Publication number: 20120306045
    Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 6, 2012
    Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner