Active Tiling Placement for Improved Latch-up Immunity
A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming, a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
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1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the use of tiling features to improve latch-up immunity of an integrated circuit.
2. Description of the Related Art
Latch-up is the condition where parasitic devices inherent in many CMOS structures cause the CMOS structure to enter an electrical state unrelated to its normal operation. This is often manifested as an abnormal high current conduction state which may he transient, may disappear when the triggering stimulus is removed, or may be permanent in the sense that the structure becomes frozen in that state as long as power continues to be applied. Unless the current in the latch-up state is somehow limited, it can also be destructive. Unfortunately, the problem of latch-up increases as CMOS device and circuit dimensions are scaled down, requiring a chip designer to make design tradeoffs to optimize the structure in order to avoid latch-up, typically by increasing the device and/or circuit area.
Accordingly, there is a need for improved CMOS structures and methods to provide improved latch-up immunity which overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
The present invention may be understood, and its numerous objects, features and advantages obtained, when the following detailed description of a preferred embodiment is considered in conjunction with the following drawings, in which:
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.
DETAILED DESCRIPTIONA method and apparatus are described for manufacturing a semiconductor device having improved latch-up immunity by filling unused space between cells and intellectual property (IP) core areas with active the structures that are tied to a reference supply or around voltage to provide latch up protection between the cells/IP, in addition, dummy tiles used to promote uniform chemical mechanical polishing (CMP) can be converted to well ties of different polarities which are electrically connected and routed to the appropriate supply voltage, thereby forming active tile structures. As disclosed, the conversion of dummy tiles to electrically active ones for reducing latch-up risk may be implemented by covering the selected dummy tile regions with the appropriate implant layers and constructing one or more conductive routing layers to connect the converted tiles an appropriate ground or power supply voltage. In selected embodiments, a dummy tile placement algorithm is modified or reused to place additional active tiles in empty spaces between circuit areas so as to promote both CMP planarity and latch up immunity. For example, dummy active tiles may be placed or located in all non-active circuit areas. Alternatively, dummy tiles may be placed or located in an initial design pass in accordance with a CMP polish placement algorithm, and then the tile density may be increased in a defined area and possibly decreased in other areas) by surveying the defined area to determine whether its tile density meets a required threshold, and if not, additional active tiles are inserted in the layout design using an iterative process of inserting smaller and smaller active tiles until the required density threshold is met. In yet other embodiments, a CMP tile placement algorithm may be modified to address both CMP concerns and to increase latch-up immunity by adding tiles in an intelligent manner based on knowledge of risk of neighboring IP blocks. As will be appreciated, the tile density may be increased by inserting any desired shape of active tiles. To provide latch-up protection, the additional active tiles are formed in a predetermined well region (e,g., PWELL/NWELL) and implanted with predetermined impurities (e.g., N+/P+ implants) to form contact regions that are connected to a predetermined supply voltage (e.g. VDD/GROUND). In an example automated design sequence, the design of the functional circuitry in the SoC integration is completed with all blocks properly connected, and then tiles are placed or located between all functional circuit areas so as to promote CMP polishing uniformity. The tiles which will improve latch-up immunity are then identified and converted to electrically active tiles by adding the appropriate implant/diffusion regions (N+P+ and possibly NW or PW) and the appropriate pins. Lastly, the design is returned through the SoC integration flow to connect the active tiles to the appropriate supply voltage. With this approach, latch-up protection is added at the SoC level as opposed to the cell/IP level by reusing active structures that are placed for CMP planarity purposes.
Various illustrative embodiments of the present invention will now be described in detail with reference to the accompanying figures. While various details are set forth in the following description, it will be appreciated that the present invention may be practiced without these specific details, and that numerous implementation-specific decisions may be made to the invention described herein to achieve the device designer's specific goals, such as compliance with process technology or design-related constraints, which will vary from one implementation to another. While such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. For example, selected aspects are depicted with reference to simplified cross sectional drawings of a semiconductor device without including every device feature or geometry in order to avoid limiting or obscuring the present invention. It is also noted that., throughout this detailed description, certain materials (such as metal tiling layers) will be formed and removed to fabricate the semiconductor structure. Where the specific procedures for forming or removing such materials are not detailed below, conventional techniques to one skilled in the art for growing, depositing, masking, etching, removing or otherwise forming such layers at appropriate thicknesses and dimensions may be used. Such details are well known and not considered necessary to teach one skilled in the art of how to make or use the present invention.
As indicated above, latch-up is a problem with many CMOS structures, especially as device and circuit dimensions shrink. Another challenge in this area is that the internal blocks in System on Chip (SoC) designs are not typically subject to the area-intensive design rules required of IO circuitry to address latch up, instead opting to prioritize density increases over addressing latch up risk. Conventionally, the risk that internal IP blocks on an SoC will he subject to noise/charge injection due to non-ideal electrical environments (e.g., at power-up events, simultaneous switching events, etc.) is addressed at the IP/cell level by including protection within the IP/cells, but no additional protection is added at the SoC integration level to address interaction between IP blocks.
Reference is now made to
While dummy tiles are drawn as “active” or OD layers during CAD design, this same layer may be used to define the electrically active tile layers described herein. Thus, in selected embodiments, the terms “tile” or “tiles” refer to the CAD process of drawing polygons of silicon which in the manufacturing process aids in CMP planarity, where “dummy tiles” refer to the tiles that are used for CMP planarity benefits without providing circuit functionality and “electrically active tiles” refer to tiles that are biased at a predetermined voltage.
One of the challenges for designing an internal chip area 10 such as shown in
In accordance with selected embodiments of the present invention, improved latch-up immunity is provided by placing additional active tiles in internal chip areas which function to tie the substrate to a power or ground supply voltage. In an example shown in
The addition of electrically active tiles not only improves latch-up immunity, but may also improve component performance for the charged device model (CDM) electrostatic discharge (ESD) events and reduce the voltage drop across the power distribution network (commonly referred to as the IR-drop). The additional substrate ties may also improve the electromagnetic compatibility (EMC) of the device by enabling the device to function without introducing intolerable electromagnetic disturbances to the environment.
In accordance with selected embodiments of the present invention, improved latch-up immunity may also be provided by replacing dummy tiles (D) with additional active tiles (A) in internal chip areas which function to tie the substrate to a power or ground supply voltage. In an example shown in
In yet other embodiments, improved latch-up immunity may also be provided by replacing dummy tiles (D) in internal chip areas with active tiles (A) so as to maintain the total number of tiles in a given chip area. In an example shown in
To illustrate an example processing sequence for fabricating active tiles, reference is now made to
To form the shallow trench isolation regions 34, one or more patterned mask layers (not shown) are formed on the substrate 32 to define shallow trench openings 33 using any desired pattern and etch techniques. For example, a patterned layer of photoresist may be formed over masking layers of oxide and/or nitride to define and remove the exposed mask layer(s) from the substrate 32. After stripping the photoresist (e.g., with an ash/piranha process), shallow trench openings 33 are formed in the semiconductor substrate 32 using any desired anisotropic etch technique, including a dry etching process such as reactive-ion etching, ion beam etching, plasma etching or laser etching, a wet etching process wherein a chemical etchant is employed or any combination thereof. After forming the shallow trench openings 33, planarized shallow trench isolation regions 34 are formed by filling the trench openings 33 with a polished insulator material, such as by depositing a dielectric material (such as high density plasma oxide), and then polishing, etching or otherwise planarizing the deposited dielectric to form the shallow trench isolation region 34, alone or in combination with additional etching, stripping and/or cleaning processes. In the course of polishing the shallow trench isolation region 34, the defined tile regions 36 serve as CMP tiles to promote planar polishing by reducing dishing. While selected embodiments are described herein with reference to example shallow trench isolation region areas, it will be appreciated that selected embodiments may be practiced with other isolation features or trench isolation regions, such as deep trench isolation regions.
It will be appreciated that additional processing steps will be used to fabricate the active tiling structures described herein, such as preparation and formation of one or more sacrificial oxide layers, deposition of one or more nitride layers, a nitride strip process, formation of liners layers in the shallow trench isolation regions, formation of various buried well or regions. In addition, other circuit features may be formed on the wafer structure, such as transistor devices which are formed with additional processing steps, including but not limited to one or more sacrificial oxide formation, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extension implant, halo implant, spacer formation, source/drain implant, heat drive or anneal steps, and polishing steps, along with conventional backend processing (not depicted), typically including formation of multiple levels of interconnect that are used to connect the transistors in a desired manner to achieve the desired functionality. Thus, the specific sequence of steps used to complete the fabrication of the semiconductor structures may vary, depending on the process and/or design requirements.
In accordance with various embodiments of the present invention, a design and fabrication methodology is provided to improve latch-up immunity by forming active tiling structures in internal or localized chip areas that are connected to a supply voltage depending on the polarity of nearby emitters. The design and placement of active tiling structures may use risk analysis to selectively prioritize the placement or conversion of CMP tiles based on circuit design considerations for nearby circuit blocks.
As depicted, the methodology begins at step 91, where the circuit design floor plan for the system is developed or received. Generally speaking, a floor plan of an integrated circuit is a simplified physical representation of tentative placement of the major functional circuit blocks. In modern electronic design process, floor plans are created during the floor planning design stage, an early stage in the hierarchical approach to chip design.
At step 92, the signal and supply routing is designed to establish the metal interconnect paths for providing signals and supply voltages (e.g., ground and power) to the functional circuit blocks. The routing step 92 is shown as being separate from the floor plan design step 91, but this is not necessarily the case. Alternatively, the routing step 92 may not occur at this stage of the design process, but may instead occur later at step 96 (described below).
At step 93, the CMP tiles are placed or located on the chip. As will be appreciated, existing tile placement algorithms can be used to identify locations on the SoC where CMP processing is likely to produce dishing and then insert CMP tiles in those locations using a predetermined tile placement scheme. At this point, the tile placement algorithm may be configured to identify unused space on the SoC between cells and IPs and then insert additional tiling features or structures that can converted and used to provide latch up protection between the cells/IP.
In order to provide latch up protection, active tiling features or structures are included in the layout design by adding active tiles and/or converting CMP tiles into active tiles having well tie structures which are connected to the appropriate supply voltage depending on the polarity of nearby emitters. This conversion process may be automated as part of the SoC integration/chip finishing process so that selected CMP tiles are converted to well tie structures and/or additional tiles are added to the SoC design. In selected embodiments, the conversion process adds active tiles to the CMP tile placement from step 93), although the design flow may also remove CMP tiles from regions where they would not be beneficial (either for latch-up or CMP), provided that additional and/or replacement active tiles are included in the tile placement such that the minimum number of total tiles (CMP and active tiles) meets or exceeds the minimum number of tiles required to meet the CMP density requirements. In
At step 95, the converted active tiles with well tie structures are prioritized for purposes of determining how each active tile will be routed. The prioritization decision may use a localized risk analysis to determine the polarity of the active tile based on the polarity of the nearby emitters in the active circuit block areas. In this way, information about nearby circuit blocks may be used to prioritize CMP tile conversion and routing of the converted well ties based on latch-up protection needs. As a result of prioritization, active tiles formed in P wells are prioritized for routing and connection to a ground reference supply voltage, while active tiles formed in N wells are prioritized for routing and connection to a power reference supply voltage. As will be appreciated, the prioritization decision may be performed earlier in the design sequence 90.
At step 96, the metal interconnect structures are designed to establish the metal interconnect paths for connecting the well tie structures in the active tiles to the corresponding reference supply voltages (e.g., ground and power) in accordance with the prioritized design. While the tie connection/routing step 96 is shown as occurring last, it will be appreciated that this step may be performed earlier in the design sequence 90.
As will be appreciated, selected embodiments of the present disclosure may be implemented as an iterative process whereby the placement and/or conversion of CMP dummy tiles to active ties and construction of routing layers uses a “loop back” process in the design flow. For example, after an initial design pass to convert, prioritize and route active ties, the design process may loop back (loop back path 98) to the CMP tile placement process (step 93) where CMP tiles are placed or located on the chip so that steps 94-96 may be repeated to convert, prioritize and route additional active ties. In addition or in the alternative, the design process may loop back. (loop back path 99) to the tile conversion process (step 94) so that additional CMP tiles may be converted, prioritized and routed to place more electrically active tiles in the layout design.
In a result of the design sequence 90, latch-up protection is added at the SoC level by re-using CMP tiling structures and/or adding new active tiling structures based on information concerning the latch-profile of surrounding active circuit blocks. In selected embodiments, the active tiling density across the SoC design or predetermined sub-partitions thereof may be increased to a predetermined tiling density threshold. In addition or in the alternative, different tiling density thresholds may be used for different zones or areas of the SoC design. For example, the initial SoC floor plan may be designed to include CMP tiles in accordance with a CMP tile placement algorithm. Then, after the CMP tiles are inserted in the SoC design, additional active tiles can be placed in empty spaces between circuit blocks or cells and converted to include well ties for improved latch-up protection.
After completion of the SoC layout design to add active tile structures for improving latch-up immunity and otherwise determine the positioning and arrangement of various layers and components of the integrated circuit, the design is then fabricated as a SoC integration/chip on a wafer. In this process, the layout design is verified, and various masks are prepared for the etch, mask, and/or implantation processes. In addition, a sequence of photographic and chemical processing steps are defined for creating the electronic circuits in the SoC design by depositing, removing, and patterning various layers, as well as modifying electrical properties of various layers. Examples of different processing steps which may be used to complete the fabrication of the SoC design include, but are not limited to, one or more semiconductor wafer or substrate formation, dielectric layer formation, substrate etching, chemical mechanical polishing, implantation and/or diffusion, silicide formation, sacrificial oxide formation, stripping, extension implant, halo implant, spacer formation, source/drain implant, source/drain anneal, contact area silicidation, and polishing steps. In addition, backend processing step may be performed to form one or more levels of interconnect to connect the active tiles to a reference voltage source in a desired manner to achieve the desired functionality. It will be appreciated that the specific sequence of steps used to complete the fabrication of the SoC design may vary, depending on the process and/or design requirements.
By now it should be appreciated that there has been provided a method for making a semiconductor device. In the disclosed methodology, a semiconductor substrate of a first conductivity type is provided which includes a plurality of tiles that are spaced apart to promote planar chemical mechanical polishing of one or more shallow trench isolation regions formed in the semiconductor substrate. As disclosed herein, the tiles may be placed to inhibit scooping from chemical mechanical planarization (CMP) and/or may be located between circuit block areas or otherwise located in close proximity to internal circuit areas at risk for latch-up. In selected embodiments, the semiconductor substrate is provided by forming at least one trench opening in the semiconductor substrate which defined by the plurality of tiles formed from the semiconductor substrate, and then depositing and planarizing an insulating material to cover the plurality of tiles and fill the trench opening(s) and form the one or more shallow trench isolation regions. At a top surface of the plurality of tiles, a plurality of well tie regions are formed of the first conductivity type, such as by implanting or diffusing heavily doped p-well regions into p-type tiles that are formed from the semiconductor substrate and have relatively lighter doping, or by implanting or diffusing heavily doped n-well regions into n-type tiles that are formed from the semiconductor substrate and have relatively lighter doping. In addition, a silicide layer may be formed on top of the well tie regions. Subsequently, a metal interconnect structure is formed in conductive or electrical contact with the plurality of well tie regions for electrically connecting the plurality of tiles to a predetermined reference voltage to provide latch-up protection. For example, tiles formed with heavily doped p-well regions are electrically connected to a ground supply voltage, while tiles formed with heavily doped n-well regions are electrically connected to a power supply voltage.
In another form, there is provided a method and system for placing active tiles in an integrated circuit design. In the disclosed embodiments, an initial circuit design floor plan is generated or received which specifies placement of a plurality of functional circuit blocks for the integrated circuit design. In the initial circuit design floor plan, a plurality of dummy tiles are placed in the according to a first tile placement algorithm which may, for example, placed the dummy tiles at locations in the initial circuit design floor plan where chemical mechanical polishing would produce dishing without the presence of the dummy tiles. In addition, a plurality of active tiles is placed in the initial circuit design floor plan according to a second tile placement algorithm to promote latch-up immunity. In selected embodiments where the dummy tiles are placed to leave empty spaces between the functional circuit blocks, the active tiles may be placed in the empty spaces between functional circuit blocks. In other embodiments, the active tiles are placed by converting one or more of the plurality of dummy tiles to active tiles in the initial circuit design floor plan according to the second tile placement algorithm. In addition or in the alternative, the active tiles may be placed by converting one or more of the plurality of dummy tiles to active tiles by taking advantage of the existing fabrication process flow for the integrated circuit design to include a highly doped region and silicide layer in each of the one or more of the plurality of dummy tiles, and then including one or more conductive routing layers for electrically connecting each of the one or more of the plurality of dummy tiles to ground or power supply voltage. The initial circuit design floor plan is also revised to electrically connect the plurality of active tiles to a supply voltage. As revised and finalized, the integrated circuit design is manufactured on a semiconductor wafer to include the plurality of active tiles which are electrically connected to a supply voltage.
In yet another form, there is provided an integrated circuit device and method for fabricating same. In the disclosed embodiments, the integrated circuit device includes a semiconductor substrate in which is formed one or more trench isolation regions. The integrated circuit device also includes a plurality of active tile structures disposed on the semiconductor substrate to prevent dishing from chemical mechanical polishing of the one or more trench isolation regions formed in the semiconductor substrate. As formed, the plurality of active tile structures each include a highly doped region located at least at a top surface, a silicide layer formed on the highly doped region, and one or more conductive routing layers electrically connected to the silicide layer and electrically connected to a predetermined supply voltage terminal, such as a ground or power supply voltage terminal. In selected embodiments, the semiconductor substrate is a p-type substrate or well, and the highly doped region is a P+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a ground supply voltage. In other embodiments, the semiconductor substrate is an a-type substrate or well, and the highly doped region is an N+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a power supply voltage. In addition, the conductive routing layers in the integrated, circuit device may be formed as a conductive contact structure or via formed in a dielectric layer to contact the silicide layer, and a supply voltage conductor layer formed over the dielectric layer to contact the conductive contact structure or via. As formed, the semiconductor substrate may include one or more active circuit regions, where the active tile structures are located outside of the active circuit regions. In addition, the integrated circuit device may include dummy tile structures disposed on the semiconductor substrate and located to prevent dishing from chemical mechanical polishing, where each dummy the structure is not electrically connected via a top surface of the dummy tile structure to the predetermined supply voltage terminal.
Although the described exemplary embodiments disclosed herein are directed to various semiconductor device structures and methods for making same, the present invention is not necessarily limited to the example embodiments which illustrate inventive aspects of the present invention that are applicable to a wide variety of semiconductor processes and/or devices. Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element orally or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims
1-13. (canceled)
14. An integrated circuit device, comprising:
- a semiconductor substrate in which is formed one or more trench isolation regions; and
- a plurality of active tile structures disposed on the semiconductor substrate to prevent dishing from chemical mechanical polishing of the one or more trench isolation regions formed in the semiconductor substrate, where the plurality of active tile structures each comprise a highly doped region located at least at a top surface, a silicide layer formed on the highly doped region, and one or more conductive routing layers electrically connected to the silicide layer and electrically connected to a predetermined supply voltage terminal, such as a power supply or ground supply voltage terminal.
15. The integrated circuit device of claim 14, where the semiconductor substrate comprises a p-type substrate or well, and the highly doped region comprises a P+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a ground supply voltage.
16. The integrated circuit device of claim 14, where the semiconductor substrate comprises an n-type substrate or well, and the highly doped region comprises an N+ region which is electrically connected through the silicide layer and the one or more conductive routing layers to a power supply voltage.
17. The integrated circuit device of claim 14, where the one or more conductive routing layers comprises:
- a conductive contact structure or via formed in a dielectric layer to contact the silicide layer; and
- a supply voltage conductor layer formed over the dielectric layer to contact the conductive contact structure or via.
18. The integrated circuit device of claim 14, further comprising one or more active circuit regions formed in the semiconductor substrate, where the plurality of active tile structures are located outside of the active circuit regions.
19. The integrated circuit device of claim 14, further comprising a plurality of dummy tile structures disposed on the semiconductor substrate, where each dummy tile structure is not electrically connected via a top surface of the dummy tile structure to the predetermined supply voltage terminal.
20. The integrated circuit device of claim 19, where the plurality of dummy tile structures are located to prevent dishing from chemical mechanical polishing.
21. An integrated circuit, comprising:
- a semiconductor substrate of a first conductivity type comprising one or more active CMOS circuit regions and one or more non-active circuit regions adjacent to the one or more active CMOS circuit regions;
- a plurality of tile structures formed in the one or more non-active circuit regions and connected to the semiconductor substrate;
- one or more isolation regions formed in the one or more non-active circuit regions of the semiconductor substrate to be substantially coplanar with the plurality of tile structures; and
- one or more metal interconnect structures for connecting the plurality of tile structures to a predetermined supply voltage of appropriate polarity, depending on a polarity of nearby emitters in the one or more active CMOS circuit regions, thereby providing latch-up protection.
22. The integrated circuit of claim 21, further comprising a plurality of well tie structures of the first conductivity type formed on the plurality of tile structures.
23. The integrated circuit of claim 21, where the one or more metal interconnect structures comprises:
- a first metal interconnect structure connected to a first plurality of well tie structures for electrically connecting a first plurality of tile structures to a first predetermined supply voltage to provide latch-up protection; and
- a second metal interconnect structure connected to a second plurality of well tie structures for electrically connecting a second plurality of tile structures to a second predetermined supply voltage to provide latch-up protection.
24. The integrated circuit of claim 21, where the semiconductor substrate comprises a p-type substrate or well, and the plurality of tile structures comprises a first plurality of highly doped P+tile structures, each of which is electrically connected through a silicide layer and one or more conductive routing layers to a ground supply voltage.
25. The integrated circuit of claim 21, where the semiconductor substrate comprises an n-type substrate or well, and the plurality of tile structures comprises a second plurality of highly doped N+ tile structures, each of which is electrically connected through a silicide layer and one or more conductive routing layers to a power supply voltage.
26. The integrated circuit of claim 23, where the first plurality of tile structures comprises N+ substrate regions located in close proximity to n-type emitter circuits in the one or more active CMOS circuit regions.
27. The integrated circuit of claim 23, where the second plurality of tile structures comprises P+substrate regions located in close proximity to p-type emitter circuits in the one or more active CMOS circuit regions.
28. The integrated circuit of claim 21, further comprising a plurality of dummy tile structures which are formed in the one or more non-active circuit regions and which are not electrically connected to a predetermined supply voltage.
29. The integrated circuit of claim 28, where the plurality of dummy tile structures are located to prevent dishing from chemical mechanical polishing of the one or more isolation regions.
30. A semiconductor device, comprising:
- a semiconductor substrate of a first conductivity type comprising one or more functional circuit regions which include parasitic NPN and PNP bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions;
- a plurality of active tiles formed on a surface of the semiconductor substrate that are spaced apart between the one or more functional circuit regions and connected to the semiconductor substrate;
- one or more chemical mechanical polished isolation regions formed on the surface of the semiconductor substrate between the one or more functional circuit regions to be substantially coplanar with the plurality of active tiles;
- a first metal interconnect structure electrically connecting a first plurality of active tiles to a first predetermined supply voltage to provide latch-up protection; and
- a second metal interconnect structure electrically connecting a second plurality of active tiles to a second predetermined supply voltage to provide latch-up protection.
31. The semiconductor device of claim 30, where the first plurality of active tiles comprises N+ substrate regions located in close proximity to n-type emitter circuits in the parasitic NPN bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions.
32. The semiconductor device of claim 30, where the second plurality of active tiles comprises P+ substrate regions located in close proximity to p-type emitter circuits in the parasitic PNP bipolar junction transistors inherent in CMOS structures formed in the one or more functional circuit regions.
33. The semiconductor device of claim 30, further comprising a plurality of dummy tile structures formed on the surface of the semiconductor substrate which are spaced apart between the one or more functional circuit regions, which are located to prevent dishing from chemical mechanical polishing of the one or more chemical mechanical polished isolation regions, and which are not electrically connected to a predetermined supply voltage.
Type: Application
Filed: May 29, 2014
Publication Date: Sep 18, 2014
Applicant: FREESCALE SEMICONDUCTOR, INC. (Austin, TX)
Inventors: Robert S. Ruth (Austin, TX), Mark A. Kearney (Austin, TX), Bernard J. Pappert (Austin, TX), Juxiang Ren (Austin, TX), Jeff L. Warner (Austin, TX)
Application Number: 14/289,730
International Classification: H01L 29/06 (20060101); H01L 23/00 (20060101); H01L 27/092 (20060101);