Abstract: A method of treating tachycardia while minimizing and/or controlling hypotension associated with such treatment includes administering a therapeutically effective amount of a pharmaceutical composition comprising the S-isomer of esmolol to a subject in need thereof.

Abstract: A pharmaceutical composition comprising (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate in a concentration between about 75 mM and about 150 mM, which is substantially free of the R-isomer or pharmaceutically acceptable salt thereof, is provided. A method of treating a cardiac disorder is also provided and includes administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical composition comprising (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate hydrochloride, wherein the (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate hydrochloride is present at a concentration between about 75 mM and about 150 mM and wherein the pharmaceutical composition is substantially free of (R)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate or pharmaceutically acceptable salt thereof.

Abstract: A method of treating tachycardia while minimizing and/or controlling hypotension associated with such treatment includes administering a therapeutically effective amount of a pharmaceutical composition comprising the S-isomer of esmolol to a subject in need thereof.

Abstract: A method of treating tachycardia while minimizing and/or controlling hypotension associated with such treatment includes administering a therapeutically effective amount of a pharmaceutical composition comprising the S-isomer of esmolol to a subject in need thereof.

Abstract: A method of treating tachycardia while minimizing and/or controlling hypotension associated with such treatment includes administering a therapeutically effective amount of a pharmaceutical composition comprising the S-isomer of esmolol to a subject in need thereof.

Abstract: A device and method for providing an optical guide of a pixel to guide incoming light to/from a photo-conversion device of the pixel to improve the optical crosstalk immunity. The optical guide includes an optically reflecting barrier formed as a trench filled with a material which produces reflection. The trench fill material may have an index of refraction that is less than the index of refraction of the material used for the trench surrounding layers to provide a light reflective structure or the trench fill material may provide a reflection surface.

Abstract: A pharmaceutical composition comprising (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate in a concentration between about 75 mM and about 150 mM, which is substantially free of the R-isomer or pharmaceutically acceptable salt thereof, is provided. A method of treating a cardiac disorder is also provided and includes administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical composition comprising (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate hydrochloride, wherein the (S)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate hydrochloride is present at a concentration between about 75 mM and about 150 mM and wherein the pharmaceutical composition is substantially free of (R)-methyl-3-[4-(2-hydroxy-3-isopropylamino)propoxy]phenylpropionate or pharmaceutically acceptable salt thereof.

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: Imager devices having an array of photosensors, each photosensor having at least two doped regions. The two doped regions are each independently tailored to a particular wavelength.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide -nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract: A photodiode has a photodiode gate structure on the surface of the substrate. The photodiode may be located in a pixel sensor cell comprising a substrate having a first surface level. The photodiode has a first doped region of a first conductivity type and a second doped region of a second conductivity type located beneath the first surface level of the substrate. A photodiode gate is formed of a first dielectric substance layer formed over the first surface of the substrate, thereby forming a second surface, and a second polysilicon layer formed over the second surface of the first layer. A transistor is located adjacent to the photodiode. The photodiode gate improves charge transfer from the photodiode to the transfer gate and floating diffusion region. The improved charge transfer minimizes image lag and leakage and reduces energy barriers.