Patents by Inventor Jeffery W. Janzen
Jeffery W. Janzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10002659Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: GrantFiled: September 14, 2016Date of Patent: June 19, 2018Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Patent number: 9607930Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: May 2, 2016Date of Patent: March 28, 2017Assignee: Micron Technologies, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Publication number: 20170004872Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: JEFFERY W. JANZEN, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Patent number: 9466344Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: GrantFiled: June 5, 2012Date of Patent: October 11, 2016Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Publication number: 20160247747Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 9343368Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: July 7, 2014Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Publication number: 20140319697Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 8772086Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: March 26, 2013Date of Patent: July 8, 2014Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 8438329Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.Type: GrantFiled: January 7, 2011Date of Patent: May 7, 2013Assignee: Micron Technology, Inc.Inventor: Jeffery W. Janzen
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Publication number: 20120309128Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffery W. Janzen, Russell D. Slifer, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 8253230Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: May 15, 2008Date of Patent: August 28, 2012Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Russell D. Slifer, legal representative, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 8205055Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: GrantFiled: June 22, 2010Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Publication number: 20120113705Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.Type: ApplicationFiled: January 12, 2012Publication date: May 10, 2012Applicant: ROUND ROCK RESEARCH, LLCInventor: Jeffery W. Janzen
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Patent number: 8174858Abstract: Systems, memory modules and methods of configuring systems including memory modules are provided. The memory modules include device parameters specifically corresponding to memory devices of the memory module. The device parameters may be retrieved from a database, and the system may be configured in accordance with the device parameters retrieved from the database.Type: GrantFiled: January 20, 2010Date of Patent: May 8, 2012Assignee: Round Rock Research, LLCInventors: Jeffery W. Janzen, Scott Schaefer, Todd D. Farrell
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Publication number: 20120036314Abstract: A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system.Type: ApplicationFiled: October 19, 2011Publication date: February 9, 2012Applicant: ROUND ROCK RESEARCH, LLCInventors: Jeffery W. Janzen, Scott Schaefer, Todd D. Farrell
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Patent number: 8098508Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.Type: GrantFiled: September 14, 2009Date of Patent: January 17, 2012Assignee: Round Rock Research, LLCInventor: Jeffery W Janzen
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Patent number: 8045415Abstract: Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for each memory device in the system.Type: GrantFiled: February 17, 2010Date of Patent: October 25, 2011Assignee: Round Rock Research, LLCInventors: Jeffery W. Janzen, Scott Schaefer, Todd D. Farrell
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Publication number: 20110103122Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Inventor: Jeffery W. Janzen
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Patent number: 7870329Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.Type: GrantFiled: May 3, 2006Date of Patent: January 11, 2011Assignee: Micron Technology, Inc.Inventor: Jeffery W. Janzen
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Publication number: 20100257332Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: ApplicationFiled: June 22, 2010Publication date: October 7, 2010Applicant: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum