DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
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This application is a divisional of U.S. application Ser. No. 12/121,654 filed May 15, 2008, now U.S. Pat. No. 8,253,230, which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThe present disclosure is directed generally to microelectronic die packages, and more particularly to stacked microelectronic dies having through-die or through-layer interconnects.
BACKGROUNDPackaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, or other microelectronic assemblies. In one conventional arrangement, the die is mounted (face down) to a supporting substrate (e.g., a printed circuit board), and the die bond pads are electrically coupled to corresponding bond pads of the substrate with metal bumps (e.g., solder balls or other suitable connections). After encapsulation, a ball-grid array on the backside of the substrate or other arrays of additional metal bumps can electrically connect the substrate to one or more external devices. Accordingly, the substrate supports the die and electrically connects the die to the external devices.
Die manufacturers have come under increasing pressure to reduce the volume occupied by the dies and yet increase the capacity of the resulting encapsulated assemblies. To meet these demands, die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within the limited surface area on the circuit board or other element to which the dies are mounted.
Various embodiments of pass-through 3D interconnects, such as through-die or through-silicon vias, and microelectronic dies and/or systems of dies that include such interconnects are described below. The term “interconnect” may encompass various types of conductive structures that extend at least partially through a substrate of a microelectronic die and electrically couple together conductive contacts located at opposing ends of the interconnect. The term “substrate” may encompass any of a variety of conductive and/or nonconductive layers (e.g., metallic, semi-conductive, and/or dielectric materials) that are situated upon and/or within one another. Such substrates can include any of a myriad of electrical devices (e.g., transistors, resistors, capacitors, etc.) or systems of such devices (e.g., an integrated circuit, a memory, a processor, etc.) formed in the conductive and/or nonconductive layers of an individual substrate.
Other embodiments of pass-through interconnects, substrates, and microelectronic dies and/or systems of dies that include such interconnects and substrates, in addition to or in lieu of the embodiments described in this section, may have several additional features or may not include many of the features shown and described below with reference to
The second die 102 can have a second substrate 110b with second contact pads 112b and a front side structure 180 having front side contacts 184 arranged in the pattern of the interconnects 120 of the first die 101. The second die 102 can also optionally include a second integrated circuit 130b electrically coupled to the second substrate pads 112b. The second substrate 110b can also be a silicon substrate or another suitable semiconductor substrate, and the second integrated circuit 130b is also shown schematically and can be within a large portion of the second substrate 110b. In many embodiments, metal bonds 166 can electrically coupled the front side contacts 184 of the second die 102 to corresponding interconnects 120 of the first die 101. In other embodiments, electrical connectors, such as solder balls, can be used in lieu of the metal bonds 166.
Referring to
Referring to
Unlike the first die 101, however, the second ESD devices 151b are not electrically isolated from an integrated circuit. The second ESD devices 151b can remain electrically coupled to the other components of the second integrated circuit 130b, and the second ESD devices 151b can also be electrically coupled to the first integrated circuit 130a via a conductive path that includes an individual contact 184, a conductive layer 185, an individual metal bond 166, and an individual interconnect 120. In other embodiments, the second ESD devices 151b can be separate components in the second die 102 that are not electrically coupled to the second integrated circuit 130b.
In general, the ESD systems 150a-b are configured to protect an integrated circuit from an ESD event. An ESD event typically involves the transfer of energy between an integrated circuit and another body that is at a different electrical potential than the integrated circuit. For example, during the manufacturing of the second die 102, an equipment operator can inadvertently touch and transfer an electrostatic potential to one of the substrate pads 112b. Without the protection of the second ESD system 150b, the transferred electrostatic potential can deliver a large electrical charge that could damage charge-sensitive portions of the second integrated circuit 130b. Even without making physical contact with a substrate pad, ESD events can also be caused by ionized ambient discharges (e.g., sparks) between a substrate pad and other charged bodies brought into close proximity with the substrate pad.
Embodiments of the ESD systems 150a-b can include circuit elements that divert potentially damaging charges away from a corresponding integrated circuit and/or charge-sensitive portions of the integrated circuit. In many embodiments, individual ESD devices include one or more diodes, metal-oxide-silicon (MOS) devices, and/or silicon-controlled rectifiers (SCRs) that are electrically coupled with a corresponding integrated circuit. In the specific embodiments of
In contrast to the system 100, conventional dies in stacked packages typically have an ESD device dedicated to each connection between a substrate pad and an integrated circuit. The ESD devices at one level of the conventional die stack are coupled to the ESD devices at another level of the conventional die stack. This creates multiple levels of ESD devices interconnected with one another. In general, a large number of ESD devices are redundant, and a single ESD device for each group of interconnected substrate pads is sufficient for protecting integrated circuits at all levels of the die stack. Removing or disabling ESD devices from only some of these dies and not others would require that the dies have a different configuration of integrated circuitry. This would accordingly require die manufacturers to fabricate separate workpieces to create the different integrated circuits. Thus, package manufacturers typically do not selectively disable or remove ESD devices. Unfortunately, as the performance of devices increases, die packages with redundant ESD devices can impair performance because the components of ESD devices typically introduce a signal delay, and intercoupling multiple ESD devices can exacerbate the signal delay.
Embodiments of the system 100, however, overcome the tradeoff between overall performance and manufacturing costs. In many embodiments, electrical connections with ESD devices can be disabled at little or no additional cost such that the system 100 does not employ redundant ESD devices. In several embodiments, the ESD devices can be selectively disable in the normal process of fabrication interconnects by forming selected interconnects through one or more metal layers, traces, and/or vias that complete the temporary conductive path between an ESD device and an integrated circuit. This process not only forms the interconnect but also removes conductive material to disconnect or otherwise disable the ESD device at the same time. In additional embodiments, electrical isolation can also be provided by a dielectric layer that separates the interconnect from the substrate.
Embodiments of the system 100 can also include a dielectric casing 198 encapsulating the first and second dies 101 and 102 and an interposer substrate 190 carrying the first and second dies 101 and 102. The interposer substrate 190, for example, can be a printed circuit board or other substrate that includes die bond pads 192 and package bond pads 194 electrically coupled to the die bond pads 192 through the interposer substrate 190. In several embodiments, individual bump bonds 196 or other electrical connectors are aligned with and attached to individual RDL contacts 144 of the first die 101 and individual die bond pads 192 of the interposer substrate 190. Accordingly, individual package bond pads 194 can provide an electrical coupling to the first integrated circuit 130a of the first die 101, the second integrated circuit 130b, and the second ESD devices 151b of the second die 102.
In many embodiments, the first metal layer 211, the second metal layer 213, the first vias 215, and the second via 217 are formed during a back end of the line (BEOL) process. For example, the first and second metal layers 211 and 213 can include aluminum, copper, or another metal that has been formed above semiconductor devices (not shown) of the integrated circuit. This metal can be patterned to define electrical connections of the integrated circuit and can include passivation layers (not shown) that separate individual levels of metal from one another. The first and second vias 215 and 217 can also be formed in a BEOL process and can include a metallic material (e.g., copper or tungsten). The vias 215 and 217 can extend through individual passivation layers to provide the electrical couplings between (a) the first and second metal layers 211 and 213 and (b) the first metal layer 211 and the first substrate pads 112b. In additional or alternative embodiments, other arrangements of vias or interconnect structures can be used to interconnect metal layers and substrate pads. For example, two or more vias can couple the first metal layer 211 to the substrate pad 144 and/or a single via can couple the first metal layer 211 to the second metal layer 213. Further, the number of vias and interconnect structures can also be based on the magnitude of a typical electrical current carried by the first metal layer 211 and/or the second metal layer 213.
Alternative manufacturing techniques can be employed in other examples of fabricating a workpiece. For example,
Embodiments of workpieces and stacked systems can also employ interconnects for electrically isolating integrated circuits and other types of circuit components, in addition to or in lieu of ESD devices. For example,
Any one of the microelectronic dies having ESD devices with disabled electrical connections described above with reference to
From the foregoing, it will be appreciated that specific embodiments have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature or additional types of other features are not precluded.
It will also be appreciated that specific embodiments have been described herein for purposes of illustration but that various modifications may be made within the claimed subject matter. For example, in addition to or in lieu of the redistribution layers, embodiments of the stacked system 100 can employ other types of intra-die electrical couplings between dies or between a die and an interposer substrate. In addition, the described methods of disabling electrical connections to ESD devices can include various modifications. Referring to
Claims
1. A method of manufacturing a stacked system of microelectronic dies, the method comprising:
- forming an interconnect through a first microelectronic die such that an electrical connection between an integrated circuit and first electrical component carried by the first die is disabled;
- aligning a second microelectronic die with the interconnect, the second die carrying a second electrical component; and
- electrically coupling the interconnect with the second electrical component of the second die.
2. The method of claim 1 wherein forming an interconnect includes forming a hole through the substrate that removes a conduction path between the integrated circuit and another circuit component carried by the first die.
3. The method of claim 1 wherein the first die includes a first metal layer and a second metal layer, and wherein forming an interconnect comprises forming a hole through the first die that removes one or more metal vias that electrically couple the first metal layer with the second metal layer.
4. The method of claim 1 wherein the first die includes a first metal layer and a second metal layer, and wherein forming an interconnect comprises forming a hole through the first die that removes conductive portions of the first metal layer and/or the second metal layer.
5. The method of claim 1 wherein the second electrical component of the second die comprises an electrostatic discharge device.
6. A method of manufacturing a microelectronic workpiece, the method comprising:
- forming a hole in a microelectronic substrate that carries a first circuit and a second circuit, the hole being formed through a conduction path in the substrate that electrically connects the first circuit with the second circuit; and
- at least partially lining a surface of the hole with a dielectric layer.
7. The method of claim 6 wherein forming a hole includes forming the hole through a metal pad that is electrically coupled to the first circuit and the second circuit, wherein the second circuit is electrically isolated from the metal pad after the hole is formed.
8. The method of claim 6 wherein forming a hole includes removing conductive material from the substrate associated with one or more metal vias of the substrate and/or one or metal layers of the substrate.
9. The method of claim 6, further comprising at least partially filling the hole with a metal, wherein the metal is adjacent to the dielectric layer.
10. The method of claim 6 wherein the second circuit comprises an electrostatic discharge device.
11. A method of manufacturing a stacked system of microelectronic dies comprising:
- disabling a first electrostatic discharge (ESD) device from first internal circuitry of a first microelectronic die;
- attaching a second microelectronic die to the first die in a stacked arrangement, wherein the second die has second internal circuitry and a second ESD device electrically coupled to the second internal circuitry, and wherein attaching the second die to the first die electrically couples the second ESD device to the first internal circuitry such that second ESD device protects the first internal circuitry and the second internal circuitry from electrostatic energy.
12. The method of claim 11 wherein the first and second ESD devices are redundant such that disabling the first ESD device reduces overall capacitive loading and improves the signal integrity of the stacked first and second dies.
13. The method of claim 12 wherein disabling the first ESD device comprises forming a hole in the first die that severs an electrical connection to the first ESD device.
14. The method of claim 13, further comprising locating the hole at a bond pad and forming a conductive through-substrate interconnect in the hole, wherein the through-substrate interconnect is electrically connected to the second ESD device but is electrically isolated from the first ESD device.
Type: Application
Filed: Aug 10, 2012
Publication Date: Dec 6, 2012
Patent Grant number: 8404521
Applicant: MICRON TECHNOLOGY, INC. (Boise, ID)
Inventors: Jeffery W. Janzen (Boise, ID), Russell D. Slifer (Boise, ID), Michael Chaine (Boise, ID), Kyle K. Kirby (Eagle, ID), William M. Hiatt (Eagle, ID)
Application Number: 13/572,461
International Classification: H01L 21/50 (20060101); H01L 21/768 (20060101);