Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.

Abstract: A method for fabricating a gate device includes forming an elongated projection (422) on a substrate (412) The elongated projection (422) protrudes from a surrounding area (424) of the substrate (412) and includes an access channel (434) for the gate device. A first terminal (430) and a second terminal (432) are formed and coupled to the access channel (434) in the elongated projection. A gate structure (522) is formed and operable to control the access channel (434) to selectively couple the first terminal (430) to the second terminal (432).

Abstract: A method for fabricating a gate device includes forming an elongated projection (422) on a substrate (412). The elongated projection (422) protrudes from a surrounding area (424) of the substrate (412) and includes an access channel (434) for the gate device. A first terminal (430) and a second terminal (432) are formed and coupled to the access channel (434) in the elongated projection. A gate structure (522) is formed and operable to control the access channel (434) to selectively couple the first terminal (430) to the second terminal (432).

Abstract: A method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the discrete post. A gate structure is formed and operable to control the access channel to selective couple the first terminal to the second terminal.

Abstract: A chemical mechanical polishing machine with ultrasonic vibration is disclosed. The chemical mechanical polishing machine (10) includes a movable abrasive surface (14). A wafer holder (12) holds a wafer (18) in contact with the abrasive surface (14), and a vibration generator (16) vibrates the wafer (18) during polishing. The ultrasonic vibration agitates the slurry and provides an additional degree of motion between the wafer and the abrasive surface, thereby increasing the speed and uniformity of the polishing.

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.

Abstract: Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.

Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.

Abstract: A contact (26) to a substrate (12) is formed using a first stopping layer (14), an insulating layer (16), and a second stopping layer (18). The second stopping layer (18) promotes a more accurate and controlled removal of the first stopping layer (14). A self-aligned contact (122) may be formed in a similar manner using a first stopping layer (110), an insulating layer (112), and a second stopping layer (114).

Abstract: A technique for quantifying the effect of plasma etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18.

Abstract: A storage node 64 of a capacitor having increased charge storage capacity and a method for forming thereof. A doped polysilicon region 68 is formed. A thin layer of hemispherical grain polysilicon 70 is deposited over the doped polysilicon region 68. The doped polysilicon region 68 and the thin layer of hemispherical grain polysilicon 70 are etched using an etch chemistry that etches the doped polysilicon region 68 faster than the thin layer of hemispherical grain polysilicon 70 to increase the surface area of an upper surface 66 of the storage node 64.

Abstract: A technique for quantifying the effect of plasma/etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18.

Abstract: A plasma flow is uniformly distributed over the surface of a water (76) by an L-shaped tube (64) and a distribution ring (62). A dispersal gas, which may either comprise an inert gas or a gas that cooperates with the reactive species of the plasma, is sprayed from the tube (64) and the ring (62) into the flow of the plasma. The ring (62) comprises a hollow tube encircling the outlet of a plasma reactor. A gas is circulated through the ring (62) within the hollow interior (66) and is emitted therefrom by nozzles (70). The tube (64) comprises a quartz or anodized aluminum L-shaped tube which is positioned directly in the flow of the plasma. The gas is emitted from the tube (64) in a direction directly opposite and into the flow of the plasma.

Abstract: A downstream remote processor (40) having a quartz waveguide (54) is cooled by at least one baffle (66). The baffle (66) comprises quartz and is fused to the waveguide (54) so as to contact an inner wall (44) of a container (42). At least one void (68, 70) is formed through baffle (66) to allow a cooling fluid to pass therethrough. The cooling fluid is injected into the container (42) by a pump (72) through an elbow shaped inlet (74). The cooling fluid passes over the waveguide (54) and through the voids (68 and 70). Through the combined effects of the baffle (66) and the cooling fluid which is circulated through the container (42), heat generated within the waveguide (54) is dissipated thus avoiding rapid deterioration thereof and greatly reducing the deposition of contaminants in the wafer (60).

Abstract: An electrode (48) for generating molecular radicals to process a semiconductor wafer (52) is contained within an enclosure (56). A vacuum pump (58) is provided to evacuate the enclosure (56). A power source (50) powers plates (60), which are separated by grounded plates (62). A gas is introduced into the electrode (48) and is excited by the power source (50). The radicals created by the excitation pass through the electrode (48) to process the wafer (52). The alternately grounded and powered electrodes (60-62) cause electrons, created by the formation of the radicals, to travel back-and-forth between the plates. A circuitous path is provided through the electrode (48) by a grating (63) having protrusions (64-66) to further decrease the number of free electrons that escape, as well as to prevent the escape of ultraviolet light.