Abstract: A permeation barrier film structure for organic electronic devices includes one or more bilayers having a hybrid permeation barrier composition. Each of the one or more bilayers includes a first region having a first composition corresponding to a first CF4—O2 Plasma Reactive Ion Etch Rate and a second region having a second composition corresponding to a second CF4—O2 Plasma Reactive Ion Etch Rate, wherein the second Etch Rate is greater than the first Etch Rate by a factor greater than 1.2 and the hybrid permeation barrier film is a homogeneous mixture of a polymeric material and a non-polymeric material, wherein the mixture is created from a single precursor material.

Abstract: Electronic devices that use desiccants for protection from moisture. The electronic devices comprise a substrate (12) and an electronic organic element (22) disposed over the top surface of the substrate. The substrate has one or more voids (14) which store desiccants (24). The voids penetrate partially or completely through the thickness of the substrate. An environmental barrier (20) is disposed over the electronic organic element and the voids. Also provided are methods for making electronic devices that use desiccants.

Abstract: A method for protecting an electronic device comprising an organic device body. The method involves the use of a hybrid layer deposited by chemical vapor deposition. The hybrid layer comprises a mixture of a polymeric material and a non-polymeric material, wherein the weight ratio of polymeric to non-polymeric material is in the range of 95:5 to 5:95, and wherein the polymeric material and the non-polymeric material are created from the same source of precursor material. Also disclosed are techniques for impeding the lateral diffusion of environmental contaminants.

Abstract: High-throughput OVJP systems and methods are provided that may use multiple flow paths having different conductances to enable deposition with relatively short lag times. A high-throughput OVJP system may include a flow tube having a cross-sectional area much larger than the diameter of one or more apertures through which source material may be expelled during deposition. Use of such a configuration may allow for deposition with reduced lag times.

Abstract: The present invention relates to structures and components for protecting organic light emitting diodes from environmental elements such as moisture and oxygen. According to a first aspect of the invention, top-emitting, high-resolution, OLED structures are provided which include a metal foil substrate; a planarization layer disposed over the metal foil substrate; an OLED stack (which includes lower and upper electrodes as well as an organic region disposed between the electrodes) disposed over the planarization layer; and a multilayer barrier region disposed over the OLED stack. A second aspect of the invention is directed to flexible, top emitting OLED structures which include the following: thin substrate region (i.e.

Abstract: Organic electronic device structures are provided, which comprise: (a) a first portion comprising a substrate and an organic electronic device region (e.g., an OLED region) disposed over the substrate; (b) a second portion comprising a cover and a getter region; and (c) a radiation-curable, pressure-sensitive adhesive layer disposed between the first and second portions and adhering the first and second portions to one another. The adhesive layer is disposed over the entire organic electronic device region and over at least a portion of the substrate. Other aspects of the present invention are directed to methods of making the above structures.

Abstract: A field emitter device formed by a veil process wherein a protective layer comprising a release layer is deposited on the gate electrode layer for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity in the dielectric material layer on a substrate, and during the formation of a field emitter element in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.

Abstract: A field emitter device formed by a veil process wherein a protective layer comprising a release layer is deposited on the gate electrode layer for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity in the dielectric material layer on a substrate, and during the formation of a field emitter element in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.

Abstract: A microelectronic field emitter device comprising a substrate, a conductive pedestal on said substrate, and an edge emitter electrode on said pedestal, wherein the edge emitter electrode comprises an emitter cap layer having an edge. The invention also contemplates a current limiter for a microelectronic field emitter device, which comprises a semi-insulating material selected from the group consisting of SiO, SiO+Cr (0 to 50% wt.), SiO2+Cr (0 to 50% wt.), SiO+Nb, Al2O3 and SixOyNz sandwiched between an electron injector and a hole injector. Another aspect of the invention relates to a microelectronic field emitter device comprising a substrate, an emitter conductor on such substrate, and a current limiter stack formed on said substrate, such stack having a top and at least one edge, a resistive strap on top of the stack, extending over the edge in electrical contact with the emitter conductor; and an emitter electrode on the current limiter stack over the resistive strap.

Abstract: A field emitter device includes a column conductor, an insulator, and a resistor structure for advantageously limiting current in a field emitter array. A wide column conductor is deposited on an insulating substrate. An insulator is laid over the column conductor. A high resistance layer is placed on the insulator and is physically isolated from the column conductor. The high resistance material may be chromium oxide or 10%-50% wt % Cr+SiO. A group of microtip electron emitters is placed over the high resistance layer. A low resistance strap interconnects the column conductor with the high resistance layer to connect in an electrical series circuit the column conductor, the high resistance layer, and the group of electron emitters. One or more layers of insulator and a gate electrode, all with cavities for the electron emitters, are laid over the high resistance material. One layer of insulator is selected from a group of materials including SiC, SiO, and Si.sub.3 N.sub.4.

Abstract: A planarization method for use during manufacture of a microelectronic field emitter device, comprising applying a glass frit slurry including glass particles in a removable base, and subsequently baking to liquify the frit.