Patents by Inventor Jeffrey B. Johnson
Jeffrey B. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106975Abstract: A system for collaborative video recording is described. The system may include a reference clock configured to track a reference time. The system may provide, to a plurality of recording devices, a synchronization code for a collaborative video recording session. The system may identify the plurality of recording devices as participants in the collaborative video recording session. The collaborative video recording session may include broadcasting one or more synchronization signals to synchronize the plurality of recording devices to the reference time tracked by the reference clock. The collaborative video recording session may include receiving a plurality of videos from the plurality of recording devices, wherein the plurality of videos comprise timestamps based on synchronization to the reference time. The collaborative video recording session may include generating a shared timeline for the plurality of videos, wherein the shared timeline synchronizes the timestamps between the plurality of videos.Type: ApplicationFiled: September 15, 2023Publication date: March 28, 2024Applicant: Apple Inc.Inventors: Robert K Molholm, Michael B Johnson, Michael C Tchao, Jeffrey A Wozniak, Vincent B Laforet, Pramod M Shantharam
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Patent number: 11894450Abstract: A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.Type: GrantFiled: March 16, 2022Date of Patent: February 6, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Shesh Mani Pandey, Jeffrey B. Johnson
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Patent number: 11749747Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.Type: GrantFiled: January 13, 2022Date of Patent: September 5, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Judson R. Holt, Vibhor Jain, Jeffrey B. Johnson, John J. Pekarik
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Publication number: 20230238428Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.Type: ApplicationFiled: January 24, 2022Publication date: July 27, 2023Inventors: Rong-Ting Liou, Man Gu, Jeffrey B. Johnson, Wang Zheng, Jagar Singh, Haiting Wang
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Publication number: 20230223463Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Inventors: Judson R. Holt, Vibhor Jain, Jeffrey B. Johnson, John J. Pekarik
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Publication number: 20230155011Abstract: A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.Type: ApplicationFiled: March 16, 2022Publication date: May 18, 2023Applicant: GlobalFoundries U.S. Inc.Inventors: Shesh Mani Pandey, Jeffrey B. Johnson
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Patent number: 11387353Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.Type: GrantFiled: June 22, 2020Date of Patent: July 12, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Jagar Singh, Sudarshan Narayanan, Alvin J. Joseph, William J. Taylor, Jr., Jeffrey B. Johnson
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Publication number: 20210399116Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: Jagar Singh, Sudarshan Narayanan, Alvin J. Joseph, William J. Taylor, JR., Jeffrey B. Johnson
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Patent number: 10482200Abstract: In one embodiment, the invention comprises: defining a first volume in a layer of a semiconductor device; calculating a probability of finding at least one dopant atom in the first volume, based on a dopant distribution of the layer; in the case that the calculated probability is equal to or greater than a pre-determined threshold, defining at least one additional volume in the layer substantially equal to the first volume; and in the case that the calculated probability is less than the pre-determined threshold: aggregating the first volume with a second volume adjacent the first volume, the second volume being substantially equal to the first volume; and recalculating a probability of finding at least one dopant atom in the aggregated first and second volumes, based on the dopant distribution of the layer.Type: GrantFiled: January 2, 2014Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Samarth Agarwal, Abhisek Dixit, Jeffrey B. Johnson
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Patent number: 10269707Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: GrantFiled: June 27, 2017Date of Patent: April 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Patent number: 10056408Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.Type: GrantFiled: October 27, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Andres Bryant, Jeffrey B. Johnson, Effendi Leobandung, Tenko Yamashita
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Publication number: 20170294385Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: ApplicationFiled: June 27, 2017Publication date: October 12, 2017Applicant: GlobalFoundries Inc.Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Patent number: 9786751Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: GrantFiled: September 13, 2016Date of Patent: October 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Publication number: 20170047350Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Inventors: Andres Bryant, Jeffrey B. Johnson, Effendi Leobandung, Tenko Yamashita
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Publication number: 20160380065Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Applicant: GlobalFoundries Inc.Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Patent number: 9525069Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.Type: GrantFiled: December 19, 2014Date of Patent: December 20, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Andres Bryant, Jeffrey B. Johnson, Effendi Leobandung, Tenko Yamashita
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Patent number: 9496394Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: GrantFiled: October 24, 2014Date of Patent: November 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Patent number: 9484269Abstract: Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.Type: GrantFiled: June 24, 2010Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Joseph Ervin, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20160118496Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.Type: ApplicationFiled: October 24, 2014Publication date: April 28, 2016Inventors: Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak
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Publication number: 20160111447Abstract: Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventors: Andres BRYANT, Brian J. GREENE, Jeffrey B. JOHNSON, Mickey H. YU