Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.

Abstract: A system includes an input/output adapter that includes a multi-source selector coupled to a flow-through input, an elastic first-in-first-out (FIFO) structure, a completion queue, and an output bus. A controller is operatively connected to the input/output adapter. The controller is operable to select the flow-through input to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure is empty. The elastic FIFO structure is selected to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure includes at least one entry. The completion queue is selected to pass through the multi-source selector to the output bus based on determining that the completion queue includes at least one entry. The flow-through input is routed into the elastic FIFO structure based on the completion queue being selected to pass through the multi-source selector to the output bus.

Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.

Abstract: A system includes an input/output adapter that includes a multi-source selector coupled to a flow-through input, an elastic first-in-first-out (FIFO) structure, a completion queue, and an output bus. A controller is operatively connected to the input/output adapter. The controller is operable to select the flow-through input to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure is empty. The elastic FIFO structure is selected to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure includes at least one entry. The completion queue is selected to pass through the multi-source selector to the output bus based on determining that the completion queue includes at least one entry. The flow-through input is routed into the elastic FIFO structure based on the completion queue being selected to pass through the multi-source selector to the output bus.

Abstract: A system includes an input/output adapter that includes a multi-source selector coupled to a flow-through input, an elastic first-in-first-out (FIFO) structure, a completion queue, and an output bus. A controller is operatively connected to the input/output adapter. The controller is operable to select the flow-through input to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure is empty. The elastic FIFO structure is selected to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure includes at least one entry. The completion queue is selected to pass through the multi-source selector to the output bus based on determining that the completion queue includes at least one entry. The flow-through input is routed into the elastic FIFO structure based on the completion queue being selected to pass through the multi-source selector to the output bus.

Abstract: Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet including completion data on a first multi-stage pipeline and a second packet including completion data on a second multi-stage pipeline in parallel. The controller shares completion update information between the first multi-stage pipeline and the second multi-stage pipeline based on determining that the completion data of the first packet and the completion data of the second packet are associated with a same request. An aspect of the completion update information is adjusted to maintain a sequential completion order in a buffer to hold the completion data of the first packet and the completion data of the second packet based on the sharing of the completion update information between the first multi-stage pipeline and the second multi-stage pipeline.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.