Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: A method of combining scattered buffer addresses into a contiguous virtual address space comprises; receiving a plurality of read completion data portions corresponding to a single read request, storing the plurality of read completion data portions in a memory device such that an individual read completion data portion is stored in an individual address of the memory device, storing a valid indicator for a memory device address which contains the individual read completion data portion in an external storage location, storing a tag indicator associated with the read request for the individual read completion portion in an external storage location associated with the memory device address containing the individual read completion data portion, storing a sequence number associated with an individual read completion data portion in an external storage location associated with the memory device address containing the individual read completion data portion; and outputting an individual read completion data port

Abstract: An incoming LAN traffic management system comprising: an I/O adapter configured to receive incoming packets from an Ethernet; a plurality of hosts coupled to the I/O adapter and each having a host buffer; a data router configured to block information received by the I/O adapter into memory locations from an SBAL associated with at least one of the plurality of hosts and in accordance with blocking parameters for the at least one of the plurality of hosts, the data router including an expiration engine configured to expire the SBAL before it is full if at least one predetermined threshold is exceeded.

Abstract: A packet that represents unknown traffic for a virtual host is received. A test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein it is discovered the packet is a broadcast (or multicast) packet. Since such packets have multiple destinations in a virtualized environment, the broadcast (or multicast) packet requires special handling and is passed to a store engine. The store engine obtains a free packet buffer from an elastic FIFO memory, moves the packet into the free packet buffer, and submits the free packet buffer back to the elastic FIFO memory. An assist engine determines and assigns connections to packets submitted to the elastic FIFO without known connections, such as broadcast (or multicast) packets. The assist engine efficiently performs this task through the use of indirect buffers, which are also obtained from and submitted back to the elastic FIFO.

Abstract: A packet that represents unknown traffic for a virtual host is received. A first test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein, if a destination connection can be determined, a second test is performed to ascertain whether or not one or more connection-specific resources required to send the packet to a virtual host memory corresponding to the destination connection are available. If a destination connection for the packet cannot be determined, the packet is passed to a store engine. If the one or more connection-specific resources are not available, the packet is passed to the store engine. The store engine obtains a free packet buffer from a FIFO memory. The store engine moves the packet into the free packet buffer and submits the free packet buffer to the elastic FIFO memory.

Abstract: A PCI Express system comprising: a PCI Express adapter; and a PCI Express root complex coupled to the PCI Express adapter, the PCI root complex including: a protocol stack coupled to the PCI express adapter and configured to transmit information to and receive information from the PCI express adapter; an application specific logic module; and a fencing module coupled between the application specific logic module and the protocol stack and configured to, when in operation, block all signals from the application specific logic module from reaching the protocol stack.

Abstract: A packet that represents unknown traffic for a virtual host is received. A first test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein, if a destination connection can be determined, a second test is performed to ascertain whether or not one or more connection-specific resources required to send the packet to a virtual host memory corresponding to the destination connection are available. If a destination connection for the packet cannot be determined, the packet is passed to a store engine. If the one or more connection-specific resources are not available, the packet is passed to the store engine. The store engine obtains a free packet buffer from a FIFO memory. The store engine moves the packet into the free packet buffer and submits the free packet buffer to the elastic FIFO memory.

Abstract: A packet that represents unknown traffic for a virtual host is received. A test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein it is discovered the packet is a broadcast (or multicast) packet. Since such packets have multiple destinations in a virtualized environment, the broadcast (or multicast) packet requires special handling and is passed to a store engine. The store engine obtains a free packet buffer from an elastic FIFO memory, moves the packet into the free packet buffer, and submits the free packet buffer back to the elastic FIFO memory. An assist engine determines and assigns connections to packets submitted to the elastic FIFO without known connections, such as broadcast (or multicast) packets. The assist engine efficiently performs this task through the use of indirect buffers, which are also obtained from and submitted back to the elastic FIFO.

Abstract: A method of combining scattered buffer addresses into a contiguous virtual address space comprises; receiving a plurality of read completion data portions corresponding to a single read request, storing the plurality of read completion data portions in a memory device such that an individual read completion data portion is stored in an individual address of the memory device, storing a valid indicator for a memory device address which contains the individual read completion data portion in an external storage location, storing a tag indicator associated with the read request for the individual read completion portion in an external storage location associated with the memory device address containing the individual read completion data portion, storing a sequence number associated with an individual read completion data portion in an external storage location associated with the memory device address containing the individual read completion data portion; and outputting an individual read completion data port

Abstract: An incoming LAN traffic management system comprising: an I/O adapter configured to receive incoming packets from an Ethernet; a plurality of hosts coupled to the I/O adapter and each having a host buffer; a data router configured to block information received by the I/O adapter into memory locations from an SBAL associated with at least one of the plurality of hosts and in accordance with blocking parameters for the at least one of the plurality of hosts, the data router including an expiration engine configured to expire the SBAL before it is full if at least one predetermined threshold is exceeded.

Abstract: A PCI Express system comprising: a PCI Express adapter; and a PCI Express root complex coupled to the PCI Express adapter, the PCI root complex including: a protocol stack coupled to the PCI express adapter and configured to transmit information to and receive information from the PCI express adapter; an application specific logic module; and a fencing module coupled between the application specific logic module and the protocol stack and configured to, when in operation, block all signals from the application specific logic module from reaching the protocol stack.