Patents by Inventor Jeffrey C. SHEARER

Jeffrey C. SHEARER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804148
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Patent number: 10796957
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Patent number: 10629698
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10586733
    Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
  • Patent number: 10446452
    Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10396181
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20190164773
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Applicant: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • Patent number: 10304692
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • Publication number: 20190157140
    Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 23, 2019
    Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
  • Patent number: 10256326
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10249753
    Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang
  • Patent number: 10224239
    Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
  • Publication number: 20190067100
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Publication number: 20190067101
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: November 16, 2017
    Publication date: February 28, 2019
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Patent number: 10204827
    Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
  • Publication number: 20180337261
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10074730
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20180122643
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 3, 2018
    Inventors: Kangguo CHENG, Ryan O. JUNG, Fee Li LIE, Jeffrey C. SHEARER, John R. SPORRE, Sean TEEHAN
  • Publication number: 20180097107
    Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
    Type: Application
    Filed: November 15, 2017
    Publication date: April 5, 2018
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang
  • Patent number: 9882048
    Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang