Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. In an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.

Abstract: Systems and methods for performing entity resolution. In some aspects, the system obtains a plurality of attributes represented in a plurality of records from one or more sources. The system generates a plurality of match vectors based on the plurality of attributes. Each match vector includes a set of attributes that match between a pair of records and a remaining set of attributes that are not required to match between the pair of records. The system processes the plurality of match vectors using an entity resolution model trained to output a binary indicator regarding whether one or more pairs of records for a match vector be merged. The system merges the one or more pairs of records for each match vector of the plurality of match vectors having a corresponding binary indicator output from the entity resolution model that pairs of records for the match vector be merged.

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Abstract: A turbine shroud assembly includes a first shroud segment, a second shroud segment, and a damping strip seal. The first shroud segment has a first carrier segment arranged circumferentially at least partway around a central axis and a first blade track segment supported by the first carrier segment. The second shroud segment is arranged circumferentially adjacent the first shroud segment about the central axis. The damping strip seal extends circumferentially into the first shroud segment and the second shroud segment to block gases from passing between the first shroud segment and the second shroud segment.

Abstract: 4H-Benzo[f]imidazo [1,5-a][1,4]diazepines substituted in the 3-position with an amide or oxadiazole and their pharmaceutical compositions display efficacy to enhance cognition and may have utility in the treatment of cognitive deficiencies, such as in neurodegenerative and neuropsychiatric disorders.

Abstract: The present application provides methods for loading and unloading high capacity storage equipment to a solar power canopy. The methods and structures may include horizontal support members have mechanisms to engage corresponding mechanisms on a compartment housing the high capacity storage equipment. The mechanisms may include plates, flanged surfaces, rails, tracks, hook assemblies, and ridges. The methods and structures may include a superstructure that is coupled to an moves with respect to the solar power canopy frame. The superstructure may pivot and/or rotate to allow loading and unloading. The methods and structures also may include cabinets or cubicles sized to receive one or more compartments housing the high capacity storage equipment.

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Abstract: An assembly includes: a housing comprising a floor, a ceiling, a rear wall, a front wall, and opposed side walls that define a cavity, wherein the side walls include illuminable informational markings; an antenna; a radio residing in the cavity of the housing connected with the antenna; and a power source attached to the radio; wherein the power source is employed to illuminate the informational markings.

Abstract: An AMI/AMR in-ground meter box, including first and second side panels, each having an interior side and an exterior side; and first and second end panels, each having an interior side and an exterior side; wherein each of said side panels and end panels include a generally rectangular planar portion having a top edge, a bottom edge, a first interlocking end having a plurality of male elements and female slots, an arcuate second end having a 90-degree bend which forms a corner of the assembled meter box and terminating in an interlocking end having a plurality of male elements and female slots configured to interlock with paired male elements and female slots in said first interlocking end and with an improved adjustable bracket channel assembly for interior support.

Abstract: An antenna and antenna enclosure including a housing having a cylindrical first portion defining a hollow interior volume with an inner diameter, a cylindrical second portion defining a hollow interior portion having an inner diameter greater than the inner diameter of the first portion, and a disk disposed inside the second portion and defining a central hole. A rod is disposed in and extends through the central hole of the disk and is captured in the hollow interior volume of the cylindrical first portion. The rod defines a central opening and abuts an inner surface of the disk. A wire is arranged inside the central opening, and a cap covers the hollow interior of the cylindrical portion and engages the housing. A circuit board for the antenna is disposed on underside of the cap and connects to the wire.

Abstract: An AMI/AMR in-ground meter box, including first and second side panels, each having an interior side and an exterior side; and first and second end panels, each having an interior side and an exterior side; wherein each of said side panels and end panels include a generally rectangular planar portion having a top edge, a bottom edge, a first interlocking end having a plurality of male elements and female slots, an arcuate second end having a 90-degree bend which forms a corner of the assembled meter box and terminating in an interlocking end having a plurality of male elements and female slots configured to interlock with paired male elements and female slots in said first interlocking end.

Abstract: New formulations of clomazone are provided, as well as new methods for making formulations of clomazone. The new formulations provide improved efficacy, decreased volatility, and/or increased loading of clomazone over the clomazone formulations in the prior art.

Abstract: An assembly includes: a) a housing comprising a floor, a ceiling, a rear wall, a front wall, and opposed side walls that define a cavity, wherein the side walls include illuminable informational markings; an antenna; c) a radio residing in the cavity of the housing connected with the antenna; and d) a power source attached to the radio; wherein the power source is employed to illuminate the informational markings.

Abstract: An electrical backshell that includes a strain relief having a flexible neck connected to a jacketed data cable proximate a terminal end of the data cable, and a cylindrical portion integral with said flexible neck; a base connector configured to accept and accommodate the terminal end of the data cable; a coupling nut configured to connect with said base connector and to engage said strain relief and to bring said cylindrical portion of said strain relief into sealing engagement with said base connector, wherein when assembled, said electrical backshell provides waterproof protection for electrical connectors in underground utility meter boxes.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.