Patents by Inventor Jeffrey D. Russell

Jeffrey D. Russell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lookahead carry circuit apparatus
    Patent number: 4425623
    Abstract: Lookahead carry circuitry is provided for use with the consecutive bit stages of a digital adder whereby the computational throughput of an arithmetic logic unit can be increased (in other words reduced in time of operation). This is accomplished by reducing the number of gates required in the serial switching path to minimize the time delay for generation of carry output signals.
    Type: Grant
    Filed: July 14, 1981
    Date of Patent: January 10, 1984
    Assignee: Rockwell International Corporation
    Inventor: Jeffrey D. Russell
  • Method and apparatus for incrementing a digital word
    Patent number: 4417315
    Abstract: A circuit is presented designed specifically for use in complementary symmetry design techniques such as CMOS/SOS wherein inverting gate types are a preferred design. This design is obtained with a minimum of delay by changing gate types in the ripple carry path wherein alternating stages utilize NAND gates with the remaining ripple carry path stages using NOR gates. To accomplish this approach, the bit stages of the word utilizing the NOR gates must have the bits inverted before being applied to the incrementing circuit.
    Type: Grant
    Filed: July 14, 1981
    Date of Patent: November 22, 1983
    Assignee: Rockwell International Corporation
    Inventor: Jeffrey D. Russell
  • Efficient means for implementing many-to-one multiplexing logic in CMOS/SOS
    Patent number: 4390988
    Abstract: A circuit for multiplexing a plurality of input signals to a single output signal through the use of N and P channel FETs whereby complementary switching circuitry results in a minimization of power usage in either the active or static circuit conditions. This is accomplished by using a feedback technique and area sizing of the FETs to obtain optimum operational results in addition to the minimal power requirements.
    Type: Grant
    Filed: July 14, 1981
    Date of Patent: June 28, 1983
    Assignee: Rockwell International Corporation
    Inventors: David W. Best, Jeffrey D. Russell