Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposted over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).

Abstract: Methods, and products formed by such methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additive metallization processes. A second mask (26) is formed over portions of the first mask (24) and the interconnect (12). Sidewalls of the first mask (24) which define at least one side of side of said interconnect (12) serve to also define at least one side of said conductive pillar (16). The second mask (26) also defines at least one side of the conductive pillar (16). The conductive pillar (16) is formed by additive metal deposition processes. The conductive pillar (16) is thus self-aligned to the interconnect (12) on which it is formed.

Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer. The method includes forming an isolation trench, viewed in plan, having corners that are angled at about 45 degrees.

Abstract: A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposited over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).

Abstract: A self-aligned bipolar transistor in which an emitter polysilicon layer is used to align both an extrinsic base region and a deep collector contact. The diffused extrinsic base is separated from the diffused emitter region by an oxide sidewall segment. Doping of the extrinsic base and the emitter is achieved by diffusion from doped overlying polysilicon loayers. The resultant structure is size limited primarily by the metal pitch of the leads.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A via (64, 66, 68) comprises a conductor (45, 46, 48) having a first surface (58, 60, 62) and at least one second surface (49) that forms at least one edge (52) with the first surface (58, 60, 62). A first insulator layer (33) is formed on the first surface and defines a first area (58, 60, 62) on the conductor that is not covered by the first insulator layer (33). A second insulator layer (70) is formed over the second surface (49). The first and second insulator layers (33, 70) define a via (64, 66 and 68) to the conductor (45, 46, 48). The bottom area (58, 60, 62) of the via (64, 66, 68) is equal to the first area and is bounded in part by the edge (52).

Abstract: Methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additive metallization processes. A second mask (26) is formed over portions of the first mask (24) and the interconnect (12). Sidewalls of the first mask (24) which define at least one side of side of said interconnect (12) serve to also define at least one side of said conductive pillar (16). The second mask (26) also defines at least one side of the conductive pillar (16). The conductive pillar (16) is formed by additive metal deposition processes. The conductive pillar (16) is thus self-aligned to the interconnect (12) on which it is formed. A cladding layer of tungsten (40) can be used on the multiple layers of seed layer (22), e.g. molybdenum coated with thin copper, of copper interconnects (12/14), and of conductive pillars (16/18).