Patents by Inventor Jeffrey E. Brighton

Jeffrey E. Brighton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4842991
    Abstract: A via (64, 66, 68) comprises a conductor (45, 46, 48) having a first surface (58, 60, 62) and at least one second surface (49) that forms at least one edge (52) with the first surface (58, 60, 62). A first insulator layer (33) is formed on the first surface and defines a first area (58, 60, 62) on the conductor that is not covered by the first insulator layer (33). A second insulator layer (70) is formed over the second surface (49). The first and second insulator layers (33, 70) define a via (64, 66 and 68) to the conductor (45, 46, 48) . The bottom area (58, 60, 62) of the via (64, 66, 68) is equal to the first area and is bounded in part by the edge (52).
    Type: Grant
    Filed: July 31, 1987
    Date of Patent: June 27, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey E. Brighton
  • Patent number: 4839305
    Abstract: A self-aligned, single polysilicon transistor is fabricated using nitride spacers (26, 68) to self-align the extrinsic base regions ( 48,80). The space between the base contacts (36,76) and the emitter contacts (34,78) is defined by the width of the nitride spacer plug (26,68) less the oxide encroachment from a thermal oxidation of the underlying polysilicon.
    Type: Grant
    Filed: June 28, 1988
    Date of Patent: June 13, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey E. Brighton
  • Patent number: 4799099
    Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.
    Type: Grant
    Filed: November 19, 1986
    Date of Patent: January 17, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas P. Verret, Jeffrey E. Brighton, Deems R. Hollingsworth, Manuel L. Torreno, Jr.
  • Patent number: 4795722
    Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: January 3, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
  • Patent number: 4789885
    Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.
    Type: Grant
    Filed: February 10, 1987
    Date of Patent: December 6, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey E. Brighton, Deems R. Hollingsworth, Michael Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Charles W. Sullivan
  • Patent number: 4753709
    Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: June 28, 1988
    Assignee: Texas Instuments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton