Patents by Inventor Jeffrey Fredenburg
Jeffrey Fredenburg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11493950Abstract: A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.Type: GrantFiled: April 30, 2021Date of Patent: November 8, 2022Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Xiao Wu
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Patent number: 11496139Abstract: A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.Type: GrantFiled: April 30, 2021Date of Patent: November 8, 2022Assignee: Movellus Circuits, Inc.Inventors: Xiao Wu, Jeffrey Fredenburg
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Publication number: 20210255661Abstract: A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Inventors: Jeffrey Fredenburg, Xiao Wu
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Publication number: 20210258013Abstract: A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Inventors: Xiao Wu, Jeffrey Fredenburg
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Patent number: 11070215Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.Type: GrantFiled: March 17, 2020Date of Patent: July 20, 2021Assignee: Movellus Circuits, Inc.Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Patent number: 11070216Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.Type: GrantFiled: April 6, 2020Date of Patent: July 20, 2021Assignee: Movellus Circuits, Inc.Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Patent number: 11017138Abstract: An integrated circuit (IC) includes multiple interconnected driver cells enabled/disabled based on a first set of control signals. The multiple circuit cells are arranged to define a first aggregate enabled/disabled configuration exhibiting a first aggregated delay. The first aggregated delay is based on the individual enabled/disabled states of the circuit cells. Timing circuitry evaluates the first aggregate delay with respect to a circuit design constraint, and selectively generates a second set of control signals to configure the multiple circuit cells to define a second aggregate enabled/disabled configuration having a second aggregate delay different than the first aggregate delay.Type: GrantFiled: April 6, 2020Date of Patent: May 25, 2021Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
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Publication number: 20200304131Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.Type: ApplicationFiled: April 6, 2020Publication date: September 24, 2020Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Publication number: 20200285794Abstract: An integrated circuit (IC) includes multiple interconnected driver cells enabled/disabled based on a first set of control signals. The multiple circuit cells are arranged to define a first aggregate enabled/disabled configuration exhibiting a first aggregated delay. The first aggregated delay is based on the individual enabled/disabled states of the circuit cells. Timing circuitry evaluates the first aggregate delay with respect to a circuit design constraint, and selectively generates a second set of control signals to configure the multiple circuit cells to define a second aggregate enabled/disabled configuration having a second aggregate delay different than the first aggregate delay.Type: ApplicationFiled: April 6, 2020Publication date: September 10, 2020Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
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Patent number: 10740526Abstract: A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.Type: GrantFiled: August 11, 2017Date of Patent: August 11, 2020Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang
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Publication number: 20200235746Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.Type: ApplicationFiled: March 17, 2020Publication date: July 23, 2020Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Patent number: 10713409Abstract: An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.Type: GrantFiled: March 12, 2019Date of Patent: July 14, 2020Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang
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Patent number: 10614182Abstract: A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.Type: GrantFiled: October 19, 2016Date of Patent: April 7, 2020Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
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Patent number: 10594323Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.Type: GrantFiled: June 13, 2018Date of Patent: March 17, 2020Assignee: Movellus Circuits, Inc.Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Patent number: 10587275Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.Type: GrantFiled: December 10, 2018Date of Patent: March 10, 2020Assignee: Movellus Circuits, Inc.Inventors: Jeffrey Fredenburg, Muhammad Faisal
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Publication number: 20190386663Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.Type: ApplicationFiled: June 13, 2018Publication date: December 19, 2019Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
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Publication number: 20190213297Abstract: An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang
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Publication number: 20190190525Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.Type: ApplicationFiled: December 10, 2018Publication date: June 20, 2019Inventors: Jeffrey Fredenburg, Muhammad Faisal
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Publication number: 20190087516Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.Type: ApplicationFiled: July 24, 2018Publication date: March 21, 2019Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
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Publication number: 20190050517Abstract: A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.Type: ApplicationFiled: August 11, 2017Publication date: February 14, 2019Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang