Patents by Inventor Jeffrey Fredenburg

Jeffrey Fredenburg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Concurrently optimized system-on-chip implementation with automatic synthesis and integration
    Patent number: 10031992
    Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 24, 2018
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
  • CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC SYNTHESIS AND INTEGRATION
    Publication number: 20180181684
    Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani
  • TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITS
    Publication number: 20180107774
    Abstract: A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 19, 2018
    Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani