Abstract: A low power mode and feedback arrangement for a switching power converter. Two or more main power switches. such as transistors, transfer energy from a supply to load by their opening and closing. When the load requires a relatively low power level, this condition is detected. In response, one or more of the transistor switches is disabled from switching and the reduced power requirements of the load are handled by the remaining one or more transistor switches. As a result, switching losses are reduced. This is because parasitic gate capacitance and on-resistance associated with the disabled switches no longer consume power from the power source. The invention provides significant efficiency advantages during periods when the load draws a low level of power. This is especially useful for battery-powered devices which may operate in a low power mode for extended periods of time, such as standby mode as in a portable telephone.

Abstract: A two-stage switching regulator having low power modes responsive to load power consumption. A first stage of the regulator is a power factor correction (PFC) stage. A second stage is a pulse-width modulating (PWM) stage. When a load draws a high level of current, switching in both stages is enabled. Under certain conditions, switching in either one or both of the stages is disabled by the duty cycle for the corresponding switch falling to zero. When switching in both stages is enabled, as in a normal mode, switching in the PWM stage is then disabled in response to an error signal falling below a first error threshold. When switching in the PFC stage is enabled and switching in the PWM stage is disabled, as in a first low power mode, switching in the PFC stage is then disabled in response to a feedback voltage rising above a first feedback threshold.

Abstract: A controlled output voltage is provided for a switching mode power converter operating in the continuous conduction mode without requiring a feedback path coupled to monitor the output voltage. Instead, a voltage related to the input voltage is monitored. The monitored voltage is compared to a periodic waveform for forming a switch control signal. In the case of a buck converter operating as a voltage regulator, over each period of the periodic waveform, the periodic waveform is representative of the inverse function. In the case of a boost converter operating as a voltage regulator or buck converter operating as a bus terminator or power amplifier, over each period of the periodic waveform, the periodic waveform has a linear slope. The switch control signal controls a duty cycle of the power switches. Therefore, switching is controlled in an open loop, rather than in a closed loop.

Abstract: A circuit for providing a regulated output voltage from a buck converter without directly monitoring the output voltage. The buck converter includes a switch having a first terminal coupled to a supply voltage and a second terminal coupled to a first terminal of an inductor and to a first terminal of a resistive divider. A second terminal of the inductor is coupled to a first capacitor for forming the output voltage across the first capacitor. A voltage formed by the resistive divider is applied to an inverting input of a transconductance amplifier, while a reference voltage is applied to a non-inverting input of the transconductance amplifier. An output of the transconductance amplifier is coupled to a second capacitor for forming an error signal across the second capacitor. The error signal is representative of a difference between the output voltage and a desired output voltage because an average of the voltage formed by the resistive divider is representative of the output voltage.

Abstract: A nonlinear carrier controlled power factor correction circuit operates in the continuous and discontinuous conduction modes and provides unity power factor at the input of a power supply by only sensing the output voltage and the current flowing through a diode of a rectifier circuit. The power factor correction circuit monitors a level of current flowing through the diode and generates an integrated voltage signal representative of the level of current flowing through the diode. The integrated voltage signal is compared to a periodic, carrier waveform signal generated using a feedback signal corresponding to a level of an output voltage delivered to a load. A difference between the feedback signal and a reference signal determines the waveshape and characteristics of the carrier waveform. Preferably, leading edge modulation is used to control the duty cycle of a switch within the rectifier circuit.

Abstract: A combination PFC-PWM integrated circuit converter controller having a power factor correction stage and a pulse-width modulation stage. The power factor correction stage provides unity power factor and a regulated intermediate output voltage by sensing a current in the power factor correction circuit and by sensing the regulated intermediate output voltage in a voltage control loop. The regulated intermediate output voltage is sensed by an error amplifier that includes a current mirror. A dc supply voltage for powering the integrated circuit is generated that is representative of the regulated intermediate output voltage. The dc supply voltage is sensed for an overvoltage protection function. By sensing the intermediate regulated output voltage in the voltage control loop and by sensing the dc supply voltage for overvoltage protection, a component failure is less likely to affect both functions than if a single voltage was sensed for both functions.

Abstract: A switching mode power converter monitors the level of power supplied to a load device. The operation of a switch is controlled and used to draw power from an input source and supply power to the load device. During normal operation, the operation of the switch is triggered on every clock pulse by a triggering pulse. The duty cycle of the triggering pulse is controlled by a pulse width modulation circuit which monitors the level of power being supplied to the load device. When the power being supplied to the load falls to a predetermined light load threshold level, representing that the load device is either in a standby mode or a period of light use, the switching mode power converter will reduce the amount of power being drawn from the input source by disabling the triggering pulse for an appropriate number of pulses of the clock signal. The number of pulses skipped will depend on an amount of power being supplied to the load device and an amount of voltage stored across the capacitor.

Abstract: An oscillator for generating a varying amplitude feed forward power factor correction (PFC) modulation ramp signal includes a clock generating circuit and a ramp generating circuit. The PFC ramp signal generated by the ramp generating circuit is used within a power factor correction circuit of a switching mode power converter. The timing capacitor used within the ramp generating circuit is charged from the full wave rectified line input voltage so that the amplitude of the generated ramp output signal will follow the full wave rectified input signal, thereby maintaining the current loop bandwidth at a constant value and improving the transient response of the circuit. A one-shot circuit is coupled between the discharge transistor of the clock generating circuit and the discharge transistor of the ramp generating circuit for synchronizing the clock and ramp reference signals generated by the oscillator so that the frequency of the ramp reference signal is equal to the frequency of the clock signal.

Abstract: A synchronous switching cascade connected power converter includes a first power factor correction converter stage and a second DC to DC converter stage for generating an output voltage in response to an input voltage and current. The output voltage is controlled by a circuit which measures a level of current within the circuit, compares that level to a predetermined desired level, and develops a response elsewhere in the circuit. Leading edge modulation for the first stage and trailing edge modulation for the second stage is implemented to realize synchronous switching between the two power stages. A single reference clock signal is used to control both the power stages. The duty cycle of the first stage is varied according to the input voltage. The duty cycle of the second stage is ideally held constant at fifty percent but will vary as the input voltage to this stage varies.

Abstract: A power transfer method and apparatus for efficient transfer of power are disclosed. Input power is converted in an essentially lossless manner to an intermediate form having a voltage or current in excess of that desired at the load. The intermediate power form is split into first and second parts, where the first part of the intermediate power form approximately matches an output power form desired at an output of the power transfer apparatus and the second part represents an excess power form. The first part of the intermediate power form is transferred to the output of the power transfer apparatus and the excess part is stored. Part or all of the stored excess energy is recycled in an essentially lossless manner, converted into a form that approximately matches the output power form desired at the output of the power transfer apparatus and transferred to the output of the power transfer apparatus.