Patents by Inventor Jeffrey Herbert Fischer
Jeffrey Herbert Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9495503Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.Type: GrantFiled: February 13, 2012Date of Patent: November 15, 2016Assignee: QUALCOMM IncorporatedInventors: Jeffrey Herbert Fischer, Manish Garg, Zhongze Wang
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Patent number: 9413344Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.Type: GrantFiled: March 25, 2015Date of Patent: August 9, 2016Assignee: QUALCOMM IncorporatedInventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer
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Publication number: 20160072491Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.Type: ApplicationFiled: March 25, 2015Publication date: March 10, 2016Inventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer
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Patent number: 9196330Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.Type: GrantFiled: March 20, 2012Date of Patent: November 24, 2015Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Stephen E. Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Patent number: 9134777Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.Type: GrantFiled: June 6, 2012Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Yeshwant Nagaraj Kolla, Jeffrey Herbert Fischer, William R. Flederbach
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Patent number: 8638153Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.Type: GrantFiled: March 29, 2012Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Publication number: 20130332748Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: QUALCOMM INCORPORATEDInventors: Yeshwant Nagaraj Kolla, Jeffrey Herbert Fischer, William R. Flederbach
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Publication number: 20130257498Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Publication number: 20130182514Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.Type: ApplicationFiled: March 20, 2012Publication date: July 18, 2013Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Stephen E. Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Publication number: 20120256682Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.Type: ApplicationFiled: February 13, 2012Publication date: October 11, 2012Applicant: QUALCOMM INCOPORATEDInventors: Jeffrey Herbert Fischer, Manish Garg, Zhongze Wang
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Patent number: 8154900Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.Type: GrantFiled: September 29, 2009Date of Patent: April 10, 2012Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael Thai Thanh Phan
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Patent number: 7761774Abstract: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.Type: GrantFiled: October 28, 2005Date of Patent: July 20, 2010Assignee: QUALCOMM IncorporatedInventors: Jeffrey Herbert Fischer, Michael ThaiThanh Phan, Chiaming Chai, James Norris Dieffenderfer
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Publication number: 20100023684Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.Type: ApplicationFiled: September 29, 2009Publication date: January 28, 2010Applicant: QUALCOMM INCORPORATEDInventors: CHIAMING CHAI, JEFFREY HERBERT FISCHER, MICHAEL THAI THANH PHAN
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Patent number: 7616468Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.Type: GrantFiled: August 4, 2006Date of Patent: November 10, 2009Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Patent number: 7586772Abstract: Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.Type: GrantFiled: August 4, 2006Date of Patent: September 8, 2009Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Patent number: 7564266Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.Type: GrantFiled: June 25, 2007Date of Patent: July 21, 2009Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Jeffrey Herbert Fischer
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Publication number: 20080315919Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Jeffrey Herbert Fischer
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Publication number: 20080031033Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit comprises a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Inventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Publication number: 20080031040Abstract: Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Inventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Patent number: 7301384Abstract: A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.Type: GrantFiled: March 31, 2006Date of Patent: November 27, 2007Assignee: QUALCOMM IncorporatedInventors: Fadi Adel Hamdan, Jeffrey Herbert Fischer, William James Goodall, III