Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

Abstract: A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

Abstract: A CAMRAM capable of detecting multiple hit is disclosed. The CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.

Abstract: A CAMRAM capable of detecting multiple hit is disclosed. The CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.

Abstract: An improved structure and method of operation are provided wherein a single RAM (random access memory) can be serviced by two CAMs (content addressable memory). This is accomplished by providing first actuating circuitry operably associated with and operatively connecting a first CAM to a selected portion of the RAM and second actuating circuit associated with and operably connecting a second CAM to a second portion of the RAM. The first actuating circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read and circuitry to initiate a CAMRAM index read and index write operably responsive to given control logic. The second circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read responsive to given control logic.

Abstract: A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic node keeper device through the strobe component output, the keeper device is active or conductive only when necessary to protect against noises in the pull down network for the strobe circuit. At all other times in the course of operation of the dynamic strobe circuit, the dynamic node keeper device according to the invention is nonconductive or inactive. Thus, the dynamic strobe circuit according to the invention reduces power consumption.

Abstract: An improved structure and method of operation are provided wherein a single RAM (random access memory) can be serviced by two CAMs (content addressable memory). This is accomplished by providing first actuating circuitry operably associated with and operatively connecting a first CAM to a selected portion of the RAM and second actuating circuit associated with and operably connecting a second CAM to a second portion of the RAM. The first actuating circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read and circuitry to initiate a CAMRAM index read and index write operably responsive to given control logic. The second circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read responsive to given control logic.

Abstract: A semiconductor content addressable memory (CAM) is described that has the enhanced capability of simultaneously performing content search operations between two sets of input data and stored data. This invention utilizes a segmented ML scheme, where one long ML is separated into two parts: a SML (Segmented ML) and a main ML. The SML is for evaluation of the comparison between input A and the content stored in an array of CAM cells A, and the main ML is for evaluation of the comparison between input B and the content stored in an array of CAM cells B. A specialized circuit that ties the SML and the main ML together is provided. The SML sense & restore is utilized to sense the value on the SML, send the result to the main ML if the enable signal (enable SML) is on, and restore the SML to a precharge state, if necessary, after SML evaluation. The circuit is able to discharge the ML if the SML shows a mismatch.

Abstract: A content addressable memory (CAM) structure and method that provides a redundant scheme for an ASIC. The scheme comprises a CAM comparative means for bypassing normal encoders, including a fuse structure having a fuse address list and a “CAM row compare” structure. Redundancy is provided in “CAM Search Read” and “CAM Search Read and RAM Read” operations. Normal CAM memory address rows and redundant replacement CAM memory address rows are provided for bank addresses. A miss logic is provided for detecting a bank address miss and generating a responsive miss signal, and an “address out” logic is also provided to pass only one of a generated normal CAM memory address row, redundant replacement address row or miss signal in a bank. The method and structure can support different address sizes and different cache sizes.

Abstract: The present invention provides a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuit. The contention prevention scheme provides a circuit which includes a path circuit gated by a contention prevention circuit (CPC) and the CPC, where the CPC allows functional operation to occur without adversely affecting the functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value. With a contention prevention circuit tuned in this manner, a static logical value during functional mode is provided, indicating no contention, which avoids adversely affecting the functional timing of the path circuit.