Abstract: A temperature sensor that is insensitive to process variation and mismatch is disclosed. The temperature sensor includes a PTAT voltage generator, a sampling and gain boosting circuit, a filter and a controller. The PTAT voltage generator utilizes a plurality of current sources, each of which is in electrical communication with the same diode, or diode stack. The output of the PTAT voltage generator is sampled and amplified with the sampling and gain boosting circuit. The output of the sampling and gain boosting circuit is then filtered using a low pass filter. The selection of the current mirrors, the sampling timing and other signals are provided by the controller. In some simulations, the output from the temperature sensor was accurate to within 1.5° C., using a one temperature calibration process.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: In one embodiment, an apparatus includes: a transmit path to receive, process and output a transmit radio frequency (RF) signal, the transmit path including a first power amplifier; a receive path to receive, process and output a receive RF signal, the receive path including a first low noise amplifier (LNA); and switching circuitry coupled to the transmit path and the receive path. In a transmit mode, the switching circuitry is to cause a RF filter to couple into the transmit path to filter the transmit RF signal and cause the filtered transmit RF signal to be provided to the first power amplifier and thereafter to an antenna. In a receive mode, the switching circuitry is to cause the receive RF signal to be provided to the RF filter and the first LNA, and thereafter to be provided to a digital processor.

Abstract: In one aspect, a method comprises: initializing a front end circuit of a wireless device into a first mode in which a radio frequency (RF) signal processing path comprises a low noise amplifier (LNA) having an output coupled to an RF filter; and in response to an RF signal received in the front end circuit having a level greater than a first threshold, reconfiguring the front end circuit into a second mode in which the RF filter is coupled to an input of the LNA.

Abstract: In one aspect, a method comprises: initializing a front end circuit of a wireless device into a first mode in which a radio frequency (RF) signal processing path comprises a low noise amplifier (LNA) having an output coupled to an RF filter; and in response to an RF signal received in the front end circuit having a level greater than a first threshold, reconfiguring the front end circuit into a second mode in which the RF filter is coupled to an input of the LNA.

Abstract: In one aspect, a method comprises: reconfiguring a front end circuit of a device from a first mode having a receiver radio frequency (RF) signal processing path with a first relative order into a second mode having the receiver RF signal processing path with a different relative order; determining that a timeout period has completed; and reconfiguring the front end circuit from the second mode to the first mode in response to determining that the timeout period has completed.

Abstract: In one aspect, a method comprises: receiving, in a controller of a wireless device, at least one of a first interrupt or a second interrupt, where: the first interrupt is to indicate that a receive radio frequency (RF) signal received in a front end circuit of the wireless device is overloading at least a low noise amplifier (LNA) of the front end circuit; and the second interrupt is to indicate that the receive RF signal is overloading at least a passive network of a system on chip (SoC) of the wireless device; and in response to the at least one of the first interrupt or the second interrupt, reconfiguring the front end circuit from a first mode into a second mode, where a relative order of a receiver RF signal processing path is different in the first mode than in the second mode.

Abstract: In one aspect, a method comprises: monitoring, via at least one computer system of a central entity, performance information of a plurality of wireless devices present in a network environment remotely coupled to the central entity; updating a monitoring database based on monitoring the performance information; and causing at least some of the plurality of wireless devices to be reconfigured from a first mode to a second mode based at least in part on the performance information.

Abstract: In one aspect, a method comprises: comparing, in a comparator, a signal level of a receive radio frequency (RF) signal to a first threshold, the receive RF signal obtained from a controllable location in an RF front end circuit; and in response to the signal level of the receive RF signal exceeding the first threshold, causing the RF front end circuit to be reconfigured from a first mode in which an input to a low noise amplifier (LNA) is coupled an antenna to a second mode in which the input to the LNA is coupled to an RF filter.

Abstract: In one aspect, an apparatus includes a receive path to receive, process and output a receive radio frequency (RF) signal, the receive path comprising at least one low noise amplifier (LNA) and a plurality of signal nodes. The receive path may be configurable to operate in a plurality of modes. The apparatus also may include at least one filter to filter the receive RF signal and at least one detector circuit to detect one or more levels present at one or more of the plurality of signal nodes. The apparatus may configure an order of the at least one LNA and the at least one filter, based at least in part on the one or more levels detected in the at least one detector circuit.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A temperature sensor that is insensitive to process variation and mismatch is disclosed. The temperature sensor includes a PTAT voltage generator, a sampling and gain boosting circuit, a filter and a controller. The PTAT voltage generator utilizes a plurality of current sources, each of which is in electrical communication with the same diode, or diode stack. The output of the PTAT voltage generator is sampled and amplified with the sampling and gain boosting circuit. The output of the sampling and gain boosting circuit is then filtered using a low pass filter. The selection of the current mirrors, the sampling timing and other signals are provided by the controller. In some simulations, the output from the temperature sensor was accurate to within 1.5° C., using a one temperature calibration process.

Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

Abstract: A plurality of physically unclonable function (PUF) bit cells are surveyed by supplying a plurality of threshold control values to the PUF bit cells. Survey results associated with each of the threshold control values are evaluated to determine a threshold control pair having a positive threshold control value and a negative threshold control value among the plurality of threshold control values that results in a desired number PUF bit cells that are strong ones and that are strong zeros.

Abstract: A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry.

Abstract: Current flowing through an inductor on a primary side of a voltage converter is sensed and compared to a threshold peak current value to determine when to end an ON portion of the voltage converter. The secondary side of the voltage converter supplies an indication of output voltage for use in determining the threshold peak current value. On start-up the primary side detects when the indication of output voltage is supplied by the secondary side across on isolation channel. Prior to detecting the indicating is being supplied, the primary side uses an increasing threshold peak current as the threshold peak current value. After detection that the indication of output voltage is being provided by the secondary side, the threshold peak current value is based on the indication of the output voltage.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A plurality of physically unclonable function (PUF) bit cells are surveyed by supplying a plurality of threshold control values to the PUF bit cells. Survey results associated with each of the threshold control values are evaluated to determine a threshold control pair having a positive threshold control value and a negative threshold control value among the plurality of threshold control values that results in a desired number PUF bit cells that are strong ones and that are strong zeros.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.