Abstract: Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.

Abstract: A new class of fixed partial response targets are disclosed for use in a PRML magnetic medium read channel. The preferred embodiment exhibits an equalization response characterized by the polynomial 7+4*D−4*D2−5*D3−2*D4, where D represents the unit delay operator. This read channel target provides improved matching to the inherent magnetic channel over the known canonical class of targets (1−D)(1+D){circumflex over ( )}N, and thereby reduces equalization losses. The improved spectral matching reduces amplification of noise in the channel, thereby reducing bit-error-rates. The new class of targets also exhibits a spectral null at DC, reducing problems for offset cancellation circuitry and making the disk drive less sensitive to thermal asperities. It also exhibits a spectral depression rather than a spectral null at the Nyquist frequency, making quasi-catastrophic error sequences virtually impossible.

Abstract: A phase-locked loop (PLL) has a master circuit configured to a slave circuit. The slave circuit has a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator configured to operate as a closed-loop PLL. The master circuit has a phase detector and a charge pump that are similar to the corresponding components in the slave circuit. The master circuit is configured to receive two input signals with zero phase offset. As such, any net current charge generated by the master charge pump will be indicative of mismatch within the master phase detector and charge pump, and therefore, by analogy, indicative of mismatch within the slave phase detector and charge pump, as well. A voltage signal generated by the master circuit is applied to control the generation of currents by the slave charge pump in such a way as to compensate for static phase offset that would otherwise exist in the slave circuit.

Abstract: The present invention is an apparatus and method for increasing the density of run-length-limited (RLL) block codes without increasing error propagation. By inserting a number of uncoded bytes (M) between each coded byte, the coding density is thereby increased. Starting with an RLL code with a block length (I) which is, for example, a multiple of 8, a number (M) of uncoded bytes may be inserted between each coded byte. The resulting density is: (I+8M)/(J+8M), wherein the resulting k constraint, of the (d,k,l) constraints is increased by 8M, and the resulting l constraint is increased by 4M. For example, starting with an RLL code having a coding density of 8/9 (I=8, J=9) and constraint set of (0,4,4), inserting one uncoded byte between each coded byte (M=1) results in a coding density of 16/17 which is 5.88% greater than the original 8/9 coding density. The constraint set is also increased to (0,12,8), where k is increased by 8 and l is increased by 4.

Abstract: A ring oscillator having an even number of differential amplifier stages is disclosed wherein each stage includes a differential amplifier using two N-channel MOSFETs whose gates serve as the inputs and whose drains serve as the outputs of the stage. The sources of the two MOSFETs are connected together and to a current sink consisting of a cascoded structure of N-channel MOSFETs. The drains of each of the two N-channel MOSFETs serving as the differential amplifier are each connected to a respective current source provided by a P-channel MOSFET. All of the current sinks in the stages are connected as secondary legs of a first current mirror which establishes a current of I in the sinks. All of the current sources are connected as secondary legs of a second current mirror which attempts to establish a current of (1+.varies.)I/2 in each of the sources, where .varies. is a number greater than zero.

Abstract: A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.

Abstract: An automatic gain control circuit produces a control voltage for a digital baseband line equalizer having a ternary output signal. The circuit includes a capacitor for storing a charge to produce the control voltage, a charge circuit for charging the capacitor if the amplitude of the ternary output signal exceeds a reference voltage, and a discharging circuit for discharging the capacitor only when the ternary output signal is at a non-zero level.

Abstract: A digital data receiver and digital phase-locked loop for providing rapid acquistion and decoding of burst mode data signals, such as Manchester encoded data, without ambiguity. A 180.degree. phase mis-lock detector and phase connector is provided to eliminate any phase-lock ambiguities that may occur. The mis-lock detector utilizes a Manchester data violation detector to determine if the correct phase of sample clock from the digital phase-locked loop is being used for decoding the Manchester data. The digital phase-locked loop utilizes a digital delay line with multiple taps, the appropriate tap, corresponding to a desired phase of a reference clock, is selected as the optimal sample clock. A phase detector determines the difference in phase, measured by the number of taps of the delay line, between the sampling clock phase and the incoming data transitions. The difference is accumulated in an integrator to select the optimal sampling clock phase tap.

Abstract: A fully differential variable delay element for providing precision delays for use in digital phase-locked loops or the like. The delay in each stage is controlled by changing bias currents and the coupling of a capacitance load thereto, therby reducing the sensitivity of the delay element to electrical noise at low bias current levels (long delay times). Included is a circuit which substantially removes any skew in the differentially delayed signals from the delay element.

Abstract: An improved CMOS bandgap voltage reference in which a magnified current derived from a thermal voltage reference produces a voltage drop across a resistor. The resistor in turn couples to a single bipolar transistor which is part of the thermal voltage reference. The bandgap voltage is the sum of the voltage across the resistor and the voltage across the bipolar transistor. In addition, the immunity of a bandgap voltage reference to variations in power supply variations is improved by having a differential amplifier sense the voltages at the control current input and the output of a current mirror in the thermal voltage reference portion of the bandgap voltage reference and adjusting the power supply voltage to the thermal voltage reference until the sensed voltages are substantially the same.

Abstract: A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.