Patents by Inventor Jeffrey Lan
Jeffrey Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160093591Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Je-Hsiung Jeffrey LAN, Wenyue ZHANG, Yang DU, Yong Ju LEE, Shiqun GU, Jing XIE
-
Publication number: 20160095208Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Daeik Daniel Kim, Je-Hsiung Jeffrey Lan, Changhan Hobie Yun, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim, David Francis Berdy
-
Patent number: 9264013Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.Type: GrantFiled: September 6, 2013Date of Patent: February 16, 2016Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Matthew Michael Nowak
-
Publication number: 20150304059Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.Type: ApplicationFiled: April 8, 2015Publication date: October 22, 2015Inventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
-
Publication number: 20150287677Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.Type: ApplicationFiled: September 11, 2014Publication date: October 8, 2015Inventors: Je-Hsiung Jeffrey LAN, David Francis BERDY, Chengjie ZUO, Daeik Daniel KIM, Changhan Hobie YUN, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA, Jonghae KIM
-
Patent number: 9136574Abstract: This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x.Type: GrantFiled: June 10, 2013Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, David Francis Berdy, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka
-
Patent number: 9001031Abstract: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.Type: GrantFiled: July 30, 2012Date of Patent: April 7, 2015Assignee: QUALCOMM MEMS Technologies, Inc.Inventors: Chi Shun Lo, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Robert Paul Mikulka, Chengjie Zuo, Changhan Hobie Yun, Jonghae Kim
-
Patent number: 8970516Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.Type: GrantFiled: September 16, 2011Date of Patent: March 3, 2015Assignee: QUALCOMM MEMS Technologies, Inc.Inventors: Justin Phelps Black, Ravindra V. Shenoy, Evgeni Petrovich Gousev, Aristotele Hadjichristos, Thomas Andrew Myers, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Chi Shun Lo
-
Publication number: 20140361854Abstract: This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: Daeik Daniel Kim, David Francis Berdy, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka
-
Publication number: 20140035702Abstract: This disclosure provides implementations of filters and filter topologies, circuits, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes one or more LC resonant circuit stages. In some implementations, each LC stage includes an inductor and a capacitor. Each LC stage also has a corresponding resonant frequency. The one or more LC stages are arranged to produce an unmodified passband over a range of frequencies having a corresponding bandwidth. One or more microelectromechanical systems (MEMS) resonators are arranged with the one or more LC stages. The one or more MEMS resonators are arranged with the one or more LC stages so as to modify characteristics of the unmodified passband such that the hybrid filter produces a modified passband having a modified bandwidth and one or more other modified band characteristics.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Justin Phelps Black, Philip Jason Stephanou, Jonghae Kim, Je-Hsiung Jeffrey Lan, Sang-June Park, Changhan Hobie Yun, Chi Shun Lo, Chengjie Zuo
-
Publication number: 20140028543Abstract: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Chi Shun Lo, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Robert Paul Mikulka, Chengjie Zuo, Changhan Hobie Yun, Jonghae Kim
-
Publication number: 20130293337Abstract: This disclosure provides systems, methods, and apparatus related to inductors. In one aspect, a planar inductor may include a substrate with a spacer in the shape of a planar spiral coil on a surface of the substrate. Disposed on the spacer may be a line of metal formed as a planar inductor in the shape of the planar spiral coil. The spacer may be between the line of metal and the surface of the substrate. The spacer may elevate the line of metal above the surface of the substrate.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Chi Shun Lo, Wesley Nathaniel Allen, Jonghae Kim, Je-Hsiung Jeffrey Lan, Ravindra V. Shenoy, Justin Phelps Black, Chengjie Zuo, Changhan Hobie Yun
-
Publication number: 20130235001Abstract: This disclosure provides implementations of electromechanical systems (EMS) piezoelectric resonator structures, transformers, devices, apparatus, systems, and related processes. In one aspect, a piezoelectric resonator structure includes a first conductive electrode layer, a second conductive electrode layer, and a piezoelectric layer arranged between the first and second conductive layers. In some implementations, the surface of the piezoelectric layer adjacent to the first conductive layer is separated from the first conductive layer by a first gap, and the surface of the piezoelectric layer adjacent to the second conductive layer is separated from the second conductive layer by a second gap. In some implementations, the resonator structure further includes an encapsulation layer arranged over the second conductive layer and providing physical support to the second conductive layer.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Changhan Hobie YUN, Je-Hsiung Jeffrey LAN, Chengjie ZUO, Chi Shun LO, Jonghae KIM
-
Patent number: 8394656Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.Type: GrantFiled: July 7, 2010Date of Patent: March 12, 2013Assignee: Qualcomm MEMS Technologies, Inc.Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
-
Publication number: 20120075216Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.Type: ApplicationFiled: September 16, 2011Publication date: March 29, 2012Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.Inventors: Justin Phelps Black, Ravindra V. Shenoy, Evgeni Petrovich Gousev, Aristotele Hadjichristos, Thomas Andrew Myers, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Chi Shun Lo
-
Publication number: 20100271688Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.Type: ApplicationFiled: July 7, 2010Publication date: October 28, 2010Applicant: QUALCOMM MEMS Technologies, Inc.Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
-
Patent number: 7795061Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.Type: GrantFiled: December 29, 2005Date of Patent: September 14, 2010Assignee: Qualcomm MEMS Technologies, Inc.Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
-
Publication number: 20070155051Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa