Abstract: A phase interpolator includes a sampling circuit configured to capture samples of an output of the phase interpolator, a delay circuit configured to delay sampling by the sampling circuit, a comparator configured to provide a comparison signal that indicates whether voltage of the samples exceed a reference voltage, and a counter responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator. The phase interpolator my further include a pair of driver circuits configured to concurrently drive the output of the phase interpolator.

Abstract: A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

Abstract: A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

Abstract: A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

Abstract: A delay interpolator includes pull-up devices, wherein each of the pull-up devices is coupled between a supply rail and a node, and pull-down devices, wherein each of the pull-down devices is coupled between the node and a ground. The delay interpolator also includes a first control circuit coupled to the pull-up devices, wherein the first control circuit has a first input configured to receive a first signal, a second input configured to receive a second signal that is delayed with respect to the first signal, and a control input configured to receive a first delay code; and. The delay interpolator further includes a second control circuit coupled to the pull-down devices, wherein the second control circuit has a first input configured to receive the first signal, a second input configured to receive the second signal, and a control input configured to receive a second delay code.

Abstract: A system includes delay locked loop (DLL) including a phase detector having a first input coupled to an input of the DLL, and a first delay circuit and a second delay circuit coupled in series between the input of the DLL and a second input of the phase detector. The DLL further includes a first control circuit, wherein an input of the first control circuit is coupled to an output of the phase detector, a first output of the first control circuit is coupled to a control input of the first delay circuit, and a second output of the first control circuit is coupled to a control input of the second delay circuit. The system also includes a second control circuit having an input coupled to the first control circuit, and a slave delay circuit having a control input coupled to an output of the second control circuit.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

Abstract: A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Abstract: A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.

Abstract: A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Abstract: A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.

Abstract: A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Abstract: A bias circuit is provided that is configure to control the bias for a diode-connected transistor operating in the sub-threshold region to produce a gate-to-source voltage. A differential tuning voltage derived from the gate-to-source voltage tunes a plurality of varactors.

Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.

Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

Abstract: A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SC-CMFB circuit.