Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SC-CMFB circuit.

Abstract: Certain aspects of the present disclosure provide a high-speed AC-coupled inverter-based buffer, which may be used as a buffer for a voltage-controlled oscillator (VCO), for example. One example buffer for a VCO generally includes a first inverter stage having an input node configured to receive a first complementary signal of a differential pair, a second inverter stage having an input node configured to receive a second complementary signal of the differential pair, a biasing stage replicating the first inverter stage or the second inverter stage, wherein an output node of the biasing stage is connected with an input node of the biasing stage, a first impedance coupled between the input node of the first inverter stage and the input node of the biasing stage, and a second impedance coupled between the input node of the second inverter stage and the input node of the biasing stage.

Abstract: Exemplary embodiments are related to current generators. A device may include a first integration path for charging a first integration capacitor during a first phase and a second integration path for charging a second integration capacitor during a second phase. The first integration capacitor may be configured for charging a capacitor coupled to an amplifier during the second phase and the second integration capacitor may be configured for charging the capacitor during the first phase.

Abstract: Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.

Abstract: Exemplary embodiments are related to current generators. A device may include a first integration path for charging a first integration capacitor during a first phase and a second integration path for charging a second integration capacitor during a second phase. The first integration capacitor may be configured for charging a capacitor coupled to an amplifier during the second phase and the second integration capacitor may be configured for charging the capacitor during the first phase.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: Signal conversion is implemented employing a memory system operating as a look-up table that stores a plurality of sets of output samples associated with each of a plurality of respective input samples. The look-up table thus can generate a corresponding set of output samples in response to a given input sample, thereby emulating desired digital upsampling and delta-sigma modulation. The output samples can be aggregated, such as by multiplexing, to provide an output data stream at a desired sample rate.

Abstract: Frequency synthesis is implemented by providing a delta-sigma modulated signal associated with a selected frequency, which frequency can vary based on a selection input. The delta-sigma modulated signal is converted from the digital to analog domain. The delta-sigma modulated signal can be provided directly from memory based on the selection input or, alternatively, it can be provided by a signal generator and processed by a delta-sigma modulator to provide the delta-sigma modulated signal. The selected frequency can be varied at a high rate of speed.

Abstract: Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and/or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.

Abstract: Signal conversion is implemented employing a memory system operating as a look-up table that stores a plurality of sets of output samples associated with each of a plurality of respective input samples. The look-up table thus can generate a corresponding set of output samples in response to a given input sample, thereby emulating desired digital upsampling and delta-sigma modulation. The output samples can be aggregated, such as by multiplexing, to provide an output data stream at a desired sample rate.

Abstract: Frequency synthesis is implemented by providing a delta-sigma modulated signal associated with a selected frequency, which frequency can vary based on a selection input. The delta-sigma modulated signal is converted from the digital to analog domain. The delta-sigma modulated signal can be provided directly from memory based on the selection input or, alternatively, it can be provided by a signal generator and processed by a delta-sigma modulator to provide the delta-sigma modulated signal. The selected frequency can be varied at a high rate of speed.

Abstract: Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and/or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.