Patents by Inventor Jeffrey P. Gambino

Jeffrey P. Gambino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DUAL BOND PAD STRUCTURE FOR PHOTONICS
    Publication number: 20170125973
    Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: Jeffrey P. GAMBINO, Richard S. GRAF, Robert K. LEIDY, Jeffrey C. MALING
  • PHOTODIODE STRUCTURES
    Publication number: 20170125627
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
  • WAVEGUIDE SWITCH WITH TUNED PHOTONIC MICRORING
    Publication number: 20170123290
    Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT
    Publication number: 20170125368
    Abstract: A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is formed on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with the hollow core.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • DUAL BOND PAD STRUCTURE FOR PHOTONICS
    Publication number: 20170125974
    Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: Jeffrey P. GAMBINO, Richard S. GRAF, Robert K. LEIDY, Jeffrey C. MALING
  • PHOTODIODE STRUCTURES
    Publication number: 20170125626
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
  • NANO DEPOSITION AND ABLATION FOR THE REPAIR AND FABRICATION OF INTEGRATED CIRCUITS
    Publication number: 20170117195
    Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.
    Type: Application
    Filed: January 3, 2017
    Publication date: April 27, 2017
    Inventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
  • Plug via formation with grid features in the passivation layer
    Patent number: 9633962
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • Photodiode structures
    Patent number: 9627575
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • LOW TEMPERATURE FABRICATION OF LATERAL THIN FILM VARISTOR
    Publication number: 20170104054
    Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
    Type: Application
    Filed: December 21, 2016
    Publication date: April 13, 2017
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
  • Semiconductor structures having low resistance paths throughout a wafer
    Patent number: 9620371
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Copper wire and dielectric with air gaps
    Patent number: 9613853
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Structure to prevent solder extrusion
    Patent number: 9613921
    Abstract: A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Dual bond pad structure for photonics
    Patent number: 9608403
    Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Robert K. Leidy, Jeffrey C. Maling
  • Extrusion-resistant solder interconnect structures and methods of forming
    Patent number: 9607862
    Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Tsv wafer with improved fracture strength
    Patent number: 9607929
    Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Yoba Amoah, Jeffrey P. Gambino, Christine A. Leggett, Max L. Lifson, Charles F. Musante, Sruthi Samala, David C. Thomas
  • ELECTROSTATIC SUBSTRATE HOLDER WITH NON-PLANAR SURFACE AND METHOD OF ETCHING
    Publication number: 20170069518
    Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Brett Cucci, Thai Doan, Jeffrey P. Gambino, Rebecca K. Kelley, Jed H. Rankin, Daniel S. Vanslette
  • Method of forming a glass interposer with thermal vias
    Patent number: 9585257
    Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal, David J. Russell
  • Conductive pillar shaped for solder confinement
    Patent number: 9583451
    Abstract: Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Nano deposition and ablation for the repair and fabrication of integrated circuits
    Patent number: 9583401
    Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza