Patents by Inventor Jeffrey R. Wilcox

Jeffrey R. Wilcox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747908
    Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: August 18, 2020
    Assignee: Apple Inc.
    Inventors: Pierre-Olivier J. Martel, Jeffrey R. Wilcox, Ian P. Shaeffer, Andrew D. Myrick, Robert W. Hill, Tristan F. Schaap
  • Publication number: 20200257829
    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Manu Gulati, Joseph Sokol, Jr., Jeffrey R. Wilcox, Bernard J. Semeria, Michael J. Smith
  • Patent number: 10671762
    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 2, 2020
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Joseph Sokol, Jr., Jeffrey R. Wilcox, Bernard J. Semeria, Michael J. Smith
  • Publication number: 20200012331
    Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Joshua P. de CESARE, Jonathan J. ANDREWS, Jeffrey R. WILCOX
  • Patent number: 10423212
    Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 24, 2019
    Assignee: Apple Inc.
    Inventors: Joshua P. de Cesare, Jonathan J. Andrews, Jeffrey R. Wilcox
  • Publication number: 20190286519
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: May 7, 2019
    Publication date: September 19, 2019
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10417429
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20190179531
    Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 13, 2019
    Inventors: Joydeep Ray, Varghese George, Inder M. Sodhi, Jeffrey R. Wilcox
  • Patent number: 10318377
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 11, 2019
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Publication number: 20190114433
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor is associated with a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20190102558
    Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor is associated with a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Ezekiel T. Runyon, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Patent number: 10228861
    Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Varghese George, Inder M. Sodhi, Jeffrey R. Wilcox
  • Publication number: 20190026501
    Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
    Type: Application
    Filed: September 11, 2018
    Publication date: January 24, 2019
    Inventors: Pierre-Olivier J. Martel, Jeffrey R. Wilcox, Ian P. Shaeffer, Andrew D. Myrick, Robert W. Hill, Tristan F. Schaap
  • Publication number: 20190012484
    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
    Type: Application
    Filed: August 25, 2016
    Publication date: January 10, 2019
    Inventors: Manu Gulati, Joseph Sokol, Jr., Jeffrey R. Wilcox, Bernard J. Semeria, Michael J. Smith
  • Publication number: 20180348843
    Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.
    Type: Application
    Filed: November 17, 2017
    Publication date: December 6, 2018
    Inventors: Joshua P. de CESARE, Jonathan J. ANDREWS, Jeffrey R. WILCOX
  • Publication number: 20180349609
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20180349649
    Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Pierre-Olivier J. Martel, Jeffrey R. Wilcox, Ian P. Shaeffer, Andrew D. Myrick, Robert W. Hill, Tristan F. Schaap
  • Publication number: 20180349608
    Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Ezekiel T. Runyon, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20180314592
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10102157
    Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Noam Yosef