Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: A method and apparatus for selectively disabling sense amplifiers to reduce power consumption in a memory bus interface are disclosed. The method includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence or end of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus. According to some embodiments, the disabling of the amplification may be synchronized to an edge of a delayed data strobe signal. In some embodiments, signals associated with a double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device may be communicated over the memory bus.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract: A memory system includes a memory controller and a plurality of memory devices located on a power plane and coupled to the memory controller. The memory system further includes a sense resistor coupled to the power plane and a power source coupled to the sense resistor. The memory system further includes a measurement module that is coupled to the memory controller and that measures a power consumption of the power plane.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: One or more memory requests are stored in a request buffer. Each memory request targets a memory device in a memory system having one or more memory devices. Each memory device has a first power state and a second power state. Each memory request is issued in an order from the request buffer to the memory system. The memory device targeted by one memory request from the request buffer is identified prior to or while another memory request ahead of the one memory request is issued to the memory system and performed by the memory system. The identified memory device is placed or maintained in the second power state prior to issuing the one memory request to the memory system.

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Abstract: A memory system includes a memory controller and a plurality of memory devices located on a power plane and coupled to the memory controller. The memory system further includes a sense resistor coupled to the power plane and a power source coupled to the sense resistor.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract: A per bank closure system for use in a multi-bank memory includes a timer, an activity and a closure and closure register. The timer is used to define timing windows. The banks of the memory are mapped to bits in the activity and closure registers. Page activity occurring a timing window is tracked by setting appropriate bit(s) in the activity register and resetting appropriate bit(s) in the closure register. At the end of each timing window, page(s) that were both opened in the previous timing window and are not represented in the activity register are scheduled for closure by setting corresponding bit(s) in the closure register. Then the activity register is reset and the process is repeated.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract: A per bank page closure system for use in a multi-bank memory includes a timer, an activity register. The timer is used to define timing windows. The banks of the memory are mapped to bits in the activity and closure registers. Page activity occurring a timing window is tracked by setting appropriate bit(s) in the activity register and resetting appropriate bit(s) in the closure register. At the end of each timing window, page(s) that were both opened in the previous timing window and are not represented in the activity register are scheduled for closure by setting corresponding bit(s) in the closure register. Then the activity is reset and the process is repeated.

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.