Patents by Inventor Jeffrey Robert Perry

Jeffrey Robert Perry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for creating, modifying, and simulating electrical circuits over the internet
    Patent number: 7441219
    Abstract: The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the circuit as well as add and/or remove components in a free form manner. The schematic is displayed within a web page on the user's machine with which the user may interact. Block symbols may be used to represent at least a portion of the schematic.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: October 21, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey Robert Perry, Martin Garrison, Khang Nguyen, Richard Levin, Wanda Carol Garrett, Phillip Gibson, Benjamin H. Lee
  • Method to perform thermal simulation of an electronic circuit on a network
    Patent number: 6931369
    Abstract: A method and apparatus for thermally simulating a circuit over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally simulate the designed circuit. Many characteristics of the board may be adjusted to provide an accurate thermal simulation.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey Robert Perry, Martin Garrison, Rex L. Allison, III, Richard Levin, Phil Gibson, Vandana A. Sojrani, Khang Nguyen, Wanda Carol Garrett, John D. Perzow
  • Network-based integrated device identification and ordering system
    Patent number: 6877033
    Abstract: Techniques are provided for designing a circuit that satisfies user-specified functional requirements without the user having to obtain additional education or possess specialized software. According to one embodiment, user-specified functional requirements are received over a network from a client executing a browser. The network may be, for example, the Internet. Based on the user-specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. According to one aspect of the invention, the component and topology information is used to generate a schematic diagram that is delivered in a web page to the user over the network.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: April 5, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Wanda Carol Garrett, Martin Garrison, Jeffrey Robert Perry, Rex Liebert Allison, III, Richard Joel Levin, Vandana Sojorani
  • Method for creating, modifying, and simulating electrical circuits over the internet
    Publication number: 20040268283
    Abstract: The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the circuit as well as add and/or remove components in a free form manner. The schematic is displayed within a web page on the user's machine with which the user may interact. Block symbols may be used to represent at least a portion of the schematic.
    Type: Application
    Filed: June 24, 2003
    Publication date: December 30, 2004
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jeffrey Robert Perry, Martin Garrison, Khang Nguyen, Richard Levin, Wanda Carol Garrett, Phillip Gibson, Benjamin H. Lee
  • Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas
    Patent number: 6678877
    Abstract: A method and apparatus for PCB layout of a circuit simulated over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. The components are placed on a PC board having landing areas designed to accommodate all of the anticipated component sizes for the type of circuit being designed. The PC board may be cropped to the desired size. The PCB may be cropped automatically or manually by the user. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: January 13, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey Robert Perry, Martin Garrison, Rex L. Allison, III, Richard Levin, Phil Gibson, Vandana A. Sojrani, Khang Nguyen, Wanda Carol Garrett
  • Controllable isotropic plasma etching technique for the suppression of stringers in memory cells
    Patent number: 5705419
    Abstract: In the manufacture of memory cells, horizontal etching is controlled in a manner which prevents the formation of stringers between adjacent cells without undercutting the sidewalls of a memory cell.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: January 6, 1998
    Assignee: National Semiconductor Corp.
    Inventors: Jeffrey Robert Perry, S. M. Reza Sadjadi, Kristen Ann Luttinger